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22 Apr 2022 06:04:13 -0700 Message-ID: <503795b0-282c-2a8a-b669-5e7a0fc4a696@linux.intel.com> Date: Fri, 22 Apr 2022 21:04:11 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.8.0 Subject: Re: [PATCH v2 1/4] iommu/vt-d: Check before setting PGSNP bit in pasid table entry Content-Language: en-US To: "Tian, Kevin" , "Pan, Jacob jun" , "Raj, Ashok" , "Liu, Yi L" References: <20220421113558.3504874-1-baolu.lu@linux.intel.com> <20220421113558.3504874-2-baolu.lu@linux.intel.com> From: Lu Baolu In-Reply-To: Cc: "iommu@lists.linux-foundation.org" , "linux-kernel@vger.kernel.org" X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On 2022/4/22 10:47, Tian, Kevin wrote: >> From: Lu Baolu >> Sent: Thursday, April 21, 2022 7:36 PM >> >> The latest VT-d specification states that the PGSNP field in the pasid >> table entry should be treated as Reserved(0) for implementations not >> supporting Snoop Control (SC=0 in the Extended Capability Register). >> This adds a check before setting the field. >> >> Signed-off-by: Lu Baolu >> --- >> drivers/iommu/intel/pasid.c | 13 ++++++++++--- >> 1 file changed, 10 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c >> index f8d215d85695..5cb2daa2b8cb 100644 >> --- a/drivers/iommu/intel/pasid.c >> +++ b/drivers/iommu/intel/pasid.c >> @@ -625,8 +625,14 @@ int intel_pasid_setup_first_level(struct intel_iommu >> *iommu, >> } >> } >> >> - if (flags & PASID_FLAG_PAGE_SNOOP) >> - pasid_set_pgsnp(pte); >> + if (flags & PASID_FLAG_PAGE_SNOOP) { >> + if (ecap_sc_support(iommu->ecap)) { >> + pasid_set_pgsnp(pte); >> + } else { >> + pasid_clear_entry(pte); >> + return -EINVAL; >> + } >> + } >> >> pasid_set_domain_id(pte, did); >> pasid_set_address_width(pte, iommu->agaw); >> @@ -710,7 +716,8 @@ int intel_pasid_setup_second_level(struct >> intel_iommu *iommu, >> pasid_set_fault_enable(pte); >> pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap)); >> >> - if (domain->domain.type == IOMMU_DOMAIN_UNMANAGED) >> + if (ecap_sc_support(iommu->ecap) && >> + domain->domain.type == IOMMU_DOMAIN_UNMANAGED) >> pasid_set_pgsnp(pte); >> > This should be rebased on top of Jason's enforce coherency series > instead of blindly setting it. No matter whether it's legacy mode > where we set SNP in PTE or scalable mode where we set PGSNP > in PASID entry for entire page table, the trigger point should be > same i.e. when someone calls enforce_cache_coherency(). With Jason's enforce coherency series merged, we even don't need to set PGSNP bit of a pasid entry for second level translation. 2nd level always supports SNP in PTEs, so set PGSNP in pasid table entry is unnecessary. Any thoughts? Best regards, baolu _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu