From: Suravee Suthikulanit <suravee.suthikulpanit-5C7GfCeVMHo@public.gmane.org>
To: Shuah Khan <shuahkhan-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH 2/2 V5] iommu/amd: Add logic to decode AMD IOMMU event flag
Date: Wed, 10 Apr 2013 11:27:26 -0500 [thread overview]
Message-ID: <516592EE.8050006@amd.com> (raw)
In-Reply-To: <CAKocOOML1-=SJGyvYNGK9hyOZp3UPd2WANcWqm1Joo7V6sAQpQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On 4/10/2013 11:21 AM, Shuah Khan wrote:
> Good feature. Do you also plan to add decode logic for these flags.
> For example, RZ is only meaningful when PR=1, RW is only meaningful
> when
> PR=1, TR=0, and I=0, and so on? This additional logic will be useful.
>
> Reviewed-by: Shuah Khan<shuahkhan-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>
> -- Shuah
Additional filtering logic can also be added in the future. This will
also be important if we are planning on handling IOMMU errors.
Suravee
next prev parent reply other threads:[~2013-04-10 16:27 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-04-10 15:57 [PATCH 2/2 V5] iommu/amd: Add logic to decode AMD IOMMU event flag suravee.suthikulpanit-5C7GfCeVMHo
[not found] ` <1365609459-3378-1-git-send-email-suravee.suthikulpanit-5C7GfCeVMHo@public.gmane.org>
2013-04-10 16:21 ` Shuah Khan
[not found] ` <CAKocOOML1-=SJGyvYNGK9hyOZp3UPd2WANcWqm1Joo7V6sAQpQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2013-04-10 16:27 ` Suravee Suthikulanit [this message]
2013-04-10 16:29 ` Shuah Khan
2013-04-18 16:38 ` Suravee Suthikulanit
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