From mboxrd@z Thu Jan 1 00:00:00 1970 From: Suravee Suthikulanit Subject: Re: [PATCH 2/2 V5] iommu/amd: Add logic to decode AMD IOMMU event flag Date: Wed, 10 Apr 2013 11:27:26 -0500 Message-ID: <516592EE.8050006@amd.com> References: <1365609459-3378-1-git-send-email-suravee.suthikulpanit@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Shuah Khan Cc: iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: iommu@lists.linux-foundation.org On 4/10/2013 11:21 AM, Shuah Khan wrote: > Good feature. Do you also plan to add decode logic for these flags. > For example, RZ is only meaningful when PR=1, RW is only meaningful > when > PR=1, TR=0, and I=0, and so on? This additional logic will be useful. > > Reviewed-by: Shuah Khan > > -- Shuah Additional filtering logic can also be added in the future. This will also be important if we are planning on handling IOMMU errors. Suravee