From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Warren Subject: Re: [PATCH v2 03/22] ARM: tegra: Create a DT header defining swgroups ID Date: Tue, 16 Jul 2013 17:07:12 -0600 Message-ID: <51E5D220.1070708@wwwdotorg.org> References: <1373021097-32420-1-git-send-email-hdoyu@nvidia.com> <1373021097-32420-4-git-send-email-hdoyu@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1373021097-32420-4-git-send-email-hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Hiroshi Doyu Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: iommu@lists.linux-foundation.org On 07/05/2013 04:44 AM, Hiroshi Doyu wrote: > Create a header file to define the swgroup IDs used by the IOMMU(SMMU) > binding. "swgroup" is a group of H/W clients in Tegra SoC from S/W POV. > > This will allow the same header to be used by both device tree files, > and drivers implementing this binding, which guarantees that the two > stay in sync. This also makes device trees more readable by using names > instead of magic numbers. Why does the driver need these constants; shouldn't it simply support 0..n SW group IDs that all work the same way? Or, is there some reason for it to know the identities? > diff --git a/include/dt-bindings/memory/tegra-swgroup.h b/include/dt-bindings/memory/tegra-swgroup.h s/memory/iommu/? s/tegra-swgroup.h/tegra-smmu.h/? > +#define TEGRA_SWGROUP_AFI 0 Should this file document which values are valid for which SoCs? Should there be separate files for each SoC; I don't know if it's guaranteed that IDs won't be re-assigned between different SoCs. > +#define TEGRA_SWGROUP_BIT(x) (1ULL << TEGRA_SWGROUP_##x) > + > +#define TEGRA30_SWGROUP_ALL <0x00000000 0x000779ff> > +#define TEGRA114_SWGROUP_ALL <0x00000000 0x01b659fe> Are those 3 values needed by DT files, or just the driver?