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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by SN1PEPF00036F3F.mail.protection.outlook.com (10.167.248.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9678.18 via Frontend Transport; Sun, 8 Mar 2026 20:52:40 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sun, 8 Mar 2026 13:52:30 -0700 Received: from [10.221.136.116] (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sun, 8 Mar 2026 13:52:26 -0700 Message-ID: <54bbce49-e226-436a-bcf3-025e1455cc09@nvidia.com> Date: Sun, 8 Mar 2026 21:52:24 +0100 Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/3] iommu/arm-smmu-v3: Allow ATS to be always on To: Nicolin Chen , , , , CC: , , , , , , , , , , , , References: <0e8d1ee1557c54943dd15ff836576de4c3aa58b6.1772833963.git.nicolinc@nvidia.com> Content-Language: en-US From: Nirmoy Das In-Reply-To: <0e8d1ee1557c54943dd15ff836576de4c3aa58b6.1772833963.git.nicolinc@nvidia.com> Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: F60TIbApElZT8T64OWyIfpzjknguIeA06UVKv5g8VxIkZ8XP14CGCHEavS82D69vLwi7I23yh5eY6A9hxNhJHylHFrx+QJYVZRNPYwKxOHM2iDtYx7CFUyNEwxrCUk22I2W7uAqNGH/o6LWFC1zHhlM2NsFaEV2qlReGkdCcu1JZ/tT/PXGnEf4iw6dsqXOmILlmuPhMIGeQujq5vOZ0icORt0HN5Kqoro2QxEak7WHAU1FapqDeG1uaQPYBnxwDcxQG9IdXPXipM+7qUUhrFZaXMU5CQpSI9ERqPjYUgOkzxrXIHNGrSY91i680iCGvVo7UEVFTTT778k2SZq94tpGIWviBZ3SDycGq/kYTc4UCBJVsf2jLeibssotR4fEEffiNVnhDeg17vVUrRXEpZP/sl7OMp05gKezxH6h3tiqETyAcuaxqsvdIw8EnvDNd X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Mar 2026 20:52:40.8511 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 13a26498-1236-4ea3-0605-08de7d54a3ae X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00036F3F.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8108 On 07.03.26 00:41, Nicolin Chen wrote: > When a device's default substream attaches to an identity domain, the SMMU > driver currently sets the device's STE between two modes: > > Mode 1: Cfg=Translate, S1DSS=Bypass, EATS=1 > Mode 2: Cfg=bypass (EATS is ignored by HW) > > When there is an active PASID (non-default substream), mode 1 is used. And > when there is no PASID support or no active PASID, mode 2 is used. > > The driver will also downgrade an STE from mode 1 to mode 2, when the last > active substream becomes inactive. > > However, there are PCIe devices that demand ATS to be always on. For these > devices, their STEs have to use the mode 1 as HW ignores EATS with mode 2. > > Change the driver accordingly: > - always use the mode 1 > - never downgrade to mode 2 > - allocate and retain a CD table (see note below) > > Note that these devices might not support PASID, i.e. doing non-PASID ATS. > In such a case, the ssid_bits is set to 0. However, s1cdmax must be set to > a !0 value in order to keep the S1DSS field effective. Thus, when a master > requires ats_always_on, set its s1cdmax to minimal 1, meaning the CD table > will have a dummy entry (SSID=1) that will be never used. > > Now, for these device, arm_smmu_cdtab_allocated() will always return true, > v.s. false prior to this change. When its default substream is attached to > an IDENTITY domain, its first CD is NULL in the table, which is a totally > valid case. Thus, add "!master->ats_always_on" to the condition. > > Reviewed-by: Jonathan Cameron > Signed-off-by: Nicolin Chen Tested-by: Nirmoy Das Acked-by: Nirmoy Das > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 72 ++++++++++++++++++--- > 2 files changed, 65 insertions(+), 8 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > index 3c6d65d36164f..f966d474b61fd 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > @@ -848,6 +848,7 @@ struct arm_smmu_master { > bool ats_enabled : 1; > bool ste_ats_enabled : 1; > bool stall_enabled; > + bool ats_always_on; > unsigned int ssid_bits; > unsigned int iopf_refcount; > }; > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index 4d00d796f0783..ef98e79b4e75d 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -1482,8 +1482,11 @@ void arm_smmu_clear_cd(struct arm_smmu_master *master, ioasid_t ssid) > if (!arm_smmu_cdtab_allocated(&master->cd_table)) > return; > cdptr = arm_smmu_get_cd_ptr(master, ssid); > - if (WARN_ON(!cdptr)) > + if (!cdptr) { > + /* Only ats_always_on allows a NULL CD on default substream */ > + WARN_ON(!master->ats_always_on || ssid); > return; > + } > arm_smmu_write_cd_entry(master, ssid, cdptr, &target); > } > > @@ -1496,6 +1499,22 @@ static int arm_smmu_alloc_cd_tables(struct arm_smmu_master *master) > struct arm_smmu_ctx_desc_cfg *cd_table = &master->cd_table; > > cd_table->s1cdmax = master->ssid_bits; > + > + /* > + * When a device doesn't support PASID (non default SSID), ssid_bits is > + * set to 0. This also sets S1CDMAX to 0, which disables the substreams > + * and ignores the S1DSS field. > + * > + * On the other hand, if a device demands ATS to be always on even when > + * its default substream is IOMMU bypassed, it has to use EATS that is > + * only effective with an STE (CFG=S1translate, S1DSS=Bypass). For such > + * use cases, S1CDMAX has to be !0, in order to make use of S1DSS/EATS. > + * > + * Set S1CDMAX no lower than 1. This would add a dummy substream in the > + * CD table but it should never be used by an actual CD. > + */ > + if (master->ats_always_on) > + cd_table->s1cdmax = max_t(u8, cd_table->s1cdmax, 1); > max_contexts = 1 << cd_table->s1cdmax; > > if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB) || > @@ -3250,7 +3269,8 @@ static int arm_smmu_blocking_set_dev_pasid(struct iommu_domain *new_domain, > * When the last user of the CD table goes away downgrade the STE back > * to a non-cd_table one, by re-attaching its sid_domain. > */ > - if (!arm_smmu_ssids_in_use(&master->cd_table)) { > + if (!master->ats_always_on && > + !arm_smmu_ssids_in_use(&master->cd_table)) { > struct iommu_domain *sid_domain = > iommu_driver_get_domain_for_dev(master->dev); > > @@ -3274,6 +3294,8 @@ static void arm_smmu_attach_dev_ste(struct iommu_domain *domain, > .old_domain = old_domain, > .ssid = IOMMU_NO_PASID, > }; > + bool ats_always_on = master->ats_always_on && > + s1dss != STRTAB_STE_1_S1DSS_TERMINATE; > > /* > * Do not allow any ASID to be changed while are working on the STE, > @@ -3285,7 +3307,7 @@ static void arm_smmu_attach_dev_ste(struct iommu_domain *domain, > * If the CD table is not in use we can use the provided STE, otherwise > * we use a cdtable STE with the provided S1DSS. > */ > - if (arm_smmu_ssids_in_use(&master->cd_table)) { > + if (ats_always_on || arm_smmu_ssids_in_use(&master->cd_table)) { > /* > * If a CD table has to be present then we need to run with ATS > * on because we have to assume a PASID is using ATS. For > @@ -3581,6 +3603,40 @@ static void arm_smmu_remove_master(struct arm_smmu_master *master) > kfree(master->streams); > } > > +static int arm_smmu_master_prepare_ats(struct arm_smmu_master *master) > +{ > + bool s1p = master->smmu->features & ARM_SMMU_FEAT_TRANS_S1; > + unsigned int stu = __ffs(master->smmu->pgsize_bitmap); > + struct pci_dev *pdev = to_pci_dev(master->dev); > + int ret; > + > + if (!arm_smmu_ats_supported(master)) > + return 0; > + > + if (!pci_ats_always_on(pdev)) > + goto out_prepare; > + > + /* > + * S1DSS is required for ATS to be always on for identity domain cases. > + * However, the S1DSS field is ignored if !IDR0_S1P or !IDR1_SSIDSIZE. > + */ > + if (!s1p || !master->smmu->ssid_bits) { > + dev_info_once(master->dev, > + "SMMU doesn't support ATS to be always on\n"); > + goto out_prepare; > + } > + > + master->ats_always_on = true; > + > + ret = arm_smmu_alloc_cd_tables(master); > + if (ret) > + return ret; > + > +out_prepare: > + pci_prepare_ats(pdev, stu); > + return 0; > +} > + > static struct iommu_device *arm_smmu_probe_device(struct device *dev) > { > int ret; > @@ -3629,14 +3685,14 @@ static struct iommu_device *arm_smmu_probe_device(struct device *dev) > smmu->features & ARM_SMMU_FEAT_STALL_FORCE) > master->stall_enabled = true; > > - if (dev_is_pci(dev)) { > - unsigned int stu = __ffs(smmu->pgsize_bitmap); > - > - pci_prepare_ats(to_pci_dev(dev), stu); > - } > + ret = arm_smmu_master_prepare_ats(master); > + if (ret) > + goto err_disable_pasid; > > return &smmu->iommu; > > +err_disable_pasid: > + arm_smmu_disable_pasid(master); > err_free_master: > kfree(master); > return ERR_PTR(ret);