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[31.187.140.150]) by smtp.gmail.com with ESMTPSA id r20-20020a170906365400b0099bd1a78ef5sm4640735ejb.74.2023.09.17.00.35.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 17 Sep 2023 00:35:23 -0700 (PDT) Message-ID: <54fcf0c2-c8e2-6ee8-5f6c-4de914c56c19@linaro.org> Date: Sun, 17 Sep 2023 09:35:17 +0200 Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.15.0 Subject: Re: [PATCH v2 8/8] arm64: defconfig: enable interconnect and pinctrl for SM4450 To: Georgi Djakov , Trilok Soni , Tengfei Fan , will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, catalin.marinas@arm.com Cc: geert+renesas@glider.be, arnd@arndb.de, neil.armstrong@linaro.org, nfraprado@collabora.com, rafal@milecki.pl, peng.fan@nxp.com, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, quic_shashim@quicinc.com, quic_kaushalk@quicinc.com, quic_tdas@quicinc.com, quic_tingweiz@quicinc.com, quic_aiquny@quicinc.com, kernel@quicinc.com References: <20230915021509.25773-1-quic_tengfan@quicinc.com> <20230915021509.25773-10-quic_tengfan@quicinc.com> <8f2c9664-a2c8-50dc-8a1c-e50a071ebeb2@linaro.org> <0a34dd35-7aea-4655-4cdd-e7196a1ba52b@linaro.org> <01c020ae-a019-e4eb-14cb-64503bde05a6@quicinc.com> <212f9bfa-6d4c-bba2-60d2-272c001a4322@quicinc.com> Content-Language: en-US From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 17/09/2023 00:55, Georgi Djakov wrote: > Hi Krzysztof, > > On 16.09.23 23:32, Krzysztof Kozlowski wrote: >> On 16/09/2023 17:13, Georgi Djakov wrote: >>> >>>> >>>> Complete list here, and it is inconsistent. Latest 8550 is also =y. Do we document >>>> the reasons somewhere on why they are added as =y? >>>> >>>> CONFIG_INTERCONNECT_QCOM=y >>>> CONFIG_INTERCONNECT_QCOM_MSM8916=m >>>> CONFIG_INTERCONNECT_QCOM_MSM8996=m >>>> CONFIG_INTERCONNECT_QCOM_OSM_L3=m >>>> CONFIG_INTERCONNECT_QCOM_QCM2290=m >>>> CONFIG_INTERCONNECT_QCOM_QCS404=m >>>> CONFIG_INTERCONNECT_QCOM_SA8775P=y >>>> CONFIG_INTERCONNECT_QCOM_SC7180=y >>>> CONFIG_INTERCONNECT_QCOM_SC7280=y >>>> CONFIG_INTERCONNECT_QCOM_SC8180X=y >>>> CONFIG_INTERCONNECT_QCOM_SC8280XP=y >>>> CONFIG_INTERCONNECT_QCOM_SDM845=y >>>> CONFIG_INTERCONNECT_QCOM_SM8150=m >>>> CONFIG_INTERCONNECT_QCOM_SM8250=m >>>> CONFIG_INTERCONNECT_QCOM_SM8350=m >>>> CONFIG_INTERCONNECT_QCOM_SM8450=y >>>> CONFIG_INTERCONNECT_QCOM_SM8550=y >>> >>> If the device can boot (to console/initramfs) with =m, we go with that. >>> But if something critical like the UART depends on the interconnect >>> provider, then we make it built-in. >>> >>> On SM8550 for example, we have enabled bandwidth scaling support for QUP >>> and that's why it needs to be =y. >>> >>> It looks like on SM4450 this should be =y too. >> >> I asked why SM4450 has to be =y and there was no answer. The argument >> that SM8450 is a module, is not applicable. > > From the hardware description i see in patch 7, the serial engine depends > on some interconnect provider. But as the serial console driver is only > available as built-in, the interconnect provider also needs be built-in > for the UART device to probe and register the console. > > So the answer to your question should be that this is needed by the UART > device (at least). > > Such details of course deserve to be mentioned in the commit message of > this patch. If you mean here the debug UART with console, then it is the same valid reason as in my change for others. This should be mentioned in commit msg. Best regards, Krzysztof