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Fri, 29 Jan 2021 09:43:01 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id C4731C43463; Fri, 29 Jan 2021 09:43:00 +0000 (UTC) Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: saiprakash.ranjan) by smtp.codeaurora.org (Postfix) with ESMTPSA id 91F97C433CA; Fri, 29 Jan 2021 09:42:59 +0000 (UTC) MIME-Version: 1.0 Date: Fri, 29 Jan 2021 15:12:59 +0530 From: Sai Prakash Ranjan To: Will Deacon Subject: Re: [PATCH 2/3] iommu/io-pgtable-arm: Add IOMMU_LLC page protection flag In-Reply-To: <20210129090516.GB3998@willie-the-truck> References: <3f589e7de3f9fa93e84c83420c5270c546a0c368.1610372717.git.saiprakash.ranjan@codeaurora.org> <20210129090516.GB3998@willie-the-truck> Message-ID: <5d23fce629323bcda71594010824aad0@codeaurora.org> X-Sender: saiprakash.ranjan@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 Cc: isaacm@codeaurora.org, freedreno , David Airlie , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, Akhil P Oommen , Sean Paul , Kristian H Kristensen , dri-devel@lists.freedesktop.org, Daniel Vetter , linux-arm-msm@vger.kernel.org, Robin Murphy , linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On 2021-01-29 14:35, Will Deacon wrote: > On Mon, Jan 11, 2021 at 07:45:04PM +0530, Sai Prakash Ranjan wrote: >> Add a new page protection flag IOMMU_LLC which can be used >> by non-coherent masters to set cacheable memory attributes >> for an outer level of cache called as last-level cache or >> system cache. Initial user of this page protection flag is >> the adreno gpu and then can later be used by other clients >> such as video where this can be used for per-buffer based >> mapping. >> >> Signed-off-by: Sai Prakash Ranjan >> --- >> drivers/iommu/io-pgtable-arm.c | 3 +++ >> include/linux/iommu.h | 6 ++++++ >> 2 files changed, 9 insertions(+) >> >> diff --git a/drivers/iommu/io-pgtable-arm.c >> b/drivers/iommu/io-pgtable-arm.c >> index 7439ee7fdcdb..ebe653ef601b 100644 >> --- a/drivers/iommu/io-pgtable-arm.c >> +++ b/drivers/iommu/io-pgtable-arm.c >> @@ -415,6 +415,9 @@ static arm_lpae_iopte arm_lpae_prot_to_pte(struct >> arm_lpae_io_pgtable *data, >> else if (prot & IOMMU_CACHE) >> pte |= (ARM_LPAE_MAIR_ATTR_IDX_CACHE >> << ARM_LPAE_PTE_ATTRINDX_SHIFT); >> + else if (prot & IOMMU_LLC) >> + pte |= (ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE >> + << ARM_LPAE_PTE_ATTRINDX_SHIFT); >> } >> >> if (prot & IOMMU_CACHE) >> diff --git a/include/linux/iommu.h b/include/linux/iommu.h >> index ffaa389ea128..1f82057df531 100644 >> --- a/include/linux/iommu.h >> +++ b/include/linux/iommu.h >> @@ -31,6 +31,12 @@ >> * if the IOMMU page table format is equivalent. >> */ >> #define IOMMU_PRIV (1 << 5) >> +/* >> + * Non-coherent masters can use this page protection flag to set >> cacheable >> + * memory attributes for only a transparent outer level of cache, >> also known as >> + * the last-level or system cache. >> + */ >> +#define IOMMU_LLC (1 << 6) > > On reflection, I'm a bit worried about exposing this because I think it > will > introduce a mismatched virtual alias with the CPU (we don't even have a > MAIR > set up for this memory type). Now, we also have that issue for the PTW, > but > since we always use cache maintenance (i.e. the streaming API) for > publishing the page-tables to a non-coheren walker, it works out. > However, > if somebody expects IOMMU_LLC to be coherent with a DMA API coherent > allocation, then they're potentially in for a nasty surprise due to the > mismatched outer-cacheability attributes. > Can't we add the syscached memory type similar to what is done on android? > So I can take patch (1) as a trivial rename, but unfortunately I think > this > needs more thought before exposing it beyond the PTW. > That wouldn't be of much use, would it :) , we would be losing on perf gain for GPU usecases without the rest of the patches. Thanks, Sai -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu