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Wed, 11 Aug 2021 16:06:15 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id DD1A1C433D3; Wed, 11 Aug 2021 16:06:14 +0000 (UTC) Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: saiprakash.ranjan) by smtp.codeaurora.org (Postfix) with ESMTPSA id DC676C433F1; Wed, 11 Aug 2021 16:06:12 +0000 (UTC) MIME-Version: 1.0 Date: Wed, 11 Aug 2021 21:36:12 +0530 From: Sai Prakash Ranjan To: Robin Murphy , Will Deacon Subject: Re: [PATCHv4] iommu/arm-smmu: Optimize ->tlb_flush_walk() for qcom implementation In-Reply-To: <7be65300-632a-8626-e5da-13bc9e276763@arm.com> References: <20210811060725.25221-1-saiprakash.ranjan@codeaurora.org> <20210811103011.GD4426@willie-the-truck> <7be65300-632a-8626-e5da-13bc9e276763@arm.com> Message-ID: <746c64bffa60e18b34075f09881946e0@codeaurora.org> X-Sender: saiprakash.ranjan@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 Cc: linux-arm-msm@vger.kernel.org, Doug Anderson , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, Thierry Reding , linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On 2021-08-11 21:23, Robin Murphy wrote: > On 2021-08-11 11:30, Will Deacon wrote: >> On Wed, Aug 11, 2021 at 11:37:25AM +0530, Sai Prakash Ranjan wrote: >>> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c >>> b/drivers/iommu/arm/arm-smmu/arm-smmu.c >>> index f7da8953afbe..3904b598e0f9 100644 >>> --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c >>> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c >>> @@ -327,9 +327,16 @@ static void arm_smmu_tlb_inv_range_s2(unsigned >>> long iova, size_t size, >>> static void arm_smmu_tlb_inv_walk_s1(unsigned long iova, size_t >>> size, >>> size_t granule, void *cookie) >>> { >>> - arm_smmu_tlb_inv_range_s1(iova, size, granule, cookie, >>> - ARM_SMMU_CB_S1_TLBIVA); >>> - arm_smmu_tlb_sync_context(cookie); >>> + struct arm_smmu_domain *smmu_domain = cookie; >>> + struct arm_smmu_cfg *cfg = &smmu_domain->cfg; >>> + >>> + if (cfg->flush_walk_prefer_tlbiasid) { >>> + arm_smmu_tlb_inv_context_s1(cookie); >> >> Hmm, this introduces an unconditional wmb() if tlbiasid is preferred. >> I >> think that should be predicated on ARM_SMMU_FEAT_COHERENT_WALK like it >> is >> for the by-VA ops. Worth doing as a separate patch. >> >>> + } else { >>> + arm_smmu_tlb_inv_range_s1(iova, size, granule, cookie, >>> + ARM_SMMU_CB_S1_TLBIVA); >>> + arm_smmu_tlb_sync_context(cookie); >>> + } >>> } >>> static void arm_smmu_tlb_add_page_s1(struct iommu_iotlb_gather >>> *gather, >>> @@ -765,8 +772,10 @@ static int arm_smmu_init_domain_context(struct >>> iommu_domain *domain, >>> .iommu_dev = smmu->dev, >>> }; >>> - if (!iommu_get_dma_strict(domain)) >>> + if (!iommu_get_dma_strict(domain)) { >>> pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_NON_STRICT; >>> + cfg->flush_walk_prefer_tlbiasid = true; >> >> This is going to interact badly with Robin's series to allow dynamic >> transition to non-strict mode, as we don't have a mechanism to switch >> over to the by-ASID behaviour. Yes, it should _work_, but it's ugly >> having >> different TLBI behaviour just because of the how the domain became >> non-strict. >> >> Robin -- I think this originated from your idea at [1]. Any idea how >> to make >> it work with your other series, or shall we drop this part for now and >> leave >> the TLB invalidation behaviour the same for now? > > Yeah, I'd say drop it - I'm currently half an hour into a first > attempt at removing io_pgtable_tlb_flush_walk() entirely, which would > make it moot for non-strict anyway. > I have dropped it and sent a v5. Thanks, Sai -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu