From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yongji Xie Subject: Re: [PATCH 5/5] vfio-pci: Allow to mmap MSI-X table if interrupt remapping is supported Date: Thu, 5 May 2016 19:44:08 +0800 Message-ID: <7c8b4efd-9662-ff10-57bc-d908ac38a0bf@linux.vnet.ibm.com> References: <1461761010-5452-1-git-send-email-xyjxie@linux.vnet.ibm.com> <1461761010-5452-6-git-send-email-xyjxie@linux.vnet.ibm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: Sender: linux-pci-owner@vger.kernel.org To: "Tian, Kevin" , "kvm@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-pci@vger.kernel.org" , "linuxppc-dev@lists.ozlabs.org" , "iommu@lists.linux-foundation.org" Cc: "alex.williamson@redhat.com" , "bhelgaas@google.com" , "aik@ozlabs.ru" , "benh@kernel.crashing.org" , "paulus@samba.org" , "mpe@ellerman.id.au" , "joro@8bytes.org" , "warrier@linux.vnet.ibm.com" , "zhong@linux.vnet.ibm.com" , "nikunj@linux.vnet.ibm.com" , "eric.auger@linaro.org" , "will.deacon@arm.com" , "gwshan@linux.vnet.ibm.com" , "David.Laight@ACULAB.COM" , "alistair@popple.id.au" , "ruscur@russell.cc" List-Id: iommu@lists.linux-foundation.org On 2016/5/5 17:36, Tian, Kevin wrote: >> From: Yongji Xie >> Sent: Tuesday, May 03, 2016 3:34 PM >> >> On 2016/5/3 14:22, Tian, Kevin wrote: >> >>>> From: Yongji Xie [mailto:xyjxie@linux.vnet.ibm.com] >>>> Sent: Tuesday, May 03, 2016 2:08 PM >>>> >>>> On 2016/5/3 13:34, Tian, Kevin wrote: >>>> >>>>>> From: Yongji Xie >>>>>> Sent: Wednesday, April 27, 2016 8:43 PM >>>>>> >>>>>> This patch enables mmapping MSI-X tables if hardware supports >>>>>> interrupt remapping which can ensure that a given pci device >>>>>> can only shoot the MSIs assigned for it. >>>>>> >>>>>> With MSI-X table mmapped, we also need to expose the >>>>>> read/write interface which will be used to access MSI-X table. >>>>>> >>>>>> Signed-off-by: Yongji Xie >>>>> A curious question here. Does "allow to mmap MSI-X" essentially >>>>> mean that KVM guest can directly read/write physical MSI-X >>>>> structure then? >>>>> >>>>> Thanks >>>>> Kevin >>>>> >>>> Here we just allow to mmap MSI-X table in kernel. It doesn't >>>> mean all KVM guest can directly read/write physical MSI-X >>>> structure. This should be decided by QEMU. For PPC64 >>>> platform, we would allow to passthrough the MSI-X table >>>> because we know guest kernel would not write physical >>>> MSI-X structure when enabling MSI. >>>> >>> A bit confused here. If guest kernel doesn't need to write >>> physical MSI-X structure, what's the point of passing through >>> the table then? >> We want to allow the MSI-X table because there may be >> some critical registers in the same page as the MSI-X table. >> We have to handle the mmio access to these register in QEMU >> rather than in guest if mmapping MSI-X table is disallowed. > So you mean critical registers in same MMIO BAR as MSI-X > table, instead of two MMIO BARs in same page (the latter I > suppose with your whole patchset it won't happen then)? Yes. That's what I mean! Thanks, Yongji