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I think that worked pretty good. Sure, I can put it in the amd/iommufd.c. > >> diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h >> index 5219d7ddfdaa..efdd0cbda1df 100644 >> --- a/drivers/iommu/amd/amd_iommu_types.h >> +++ b/drivers/iommu/amd/amd_iommu_types.h >> @@ -95,9 +95,12 @@ >> #define FEATURE_HE BIT_ULL(8) >> #define FEATURE_PC BIT_ULL(9) >> #define FEATURE_HATS GENMASK_ULL(11, 10) >> +#define FEATURE_GATS_SHIFT 12 >> #define FEATURE_GATS GENMASK_ULL(13, 12) >> +#define FEATURE_GLX_SHIFT 14 >> #define FEATURE_GLX GENMASK_ULL(15, 14) >> #define FEATURE_GAM_VAPIC BIT_ULL(21) >> +#define FEATURE_PASMAX_SHIFT 32 >> #define FEATURE_PASMAX GENMASK_ULL(36, 32) > > Please no.. FIELD_PREP is how to get the shift, don't add constants. Good point. Ok >> diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c >> index eb348c63a8d0..ebe1cb9b0807 100644 >> --- a/drivers/iommu/amd/iommu.c >> +++ b/drivers/iommu/amd/iommu.c >> @@ -3038,8 +3038,48 @@ static const struct iommu_dirty_ops amd_dirty_ops = { >> .read_and_clear_dirty = amd_iommu_read_and_clear_dirty, >> }; >> >> +#define AMD_VIOMMU_EFR_GUEST_TRANSLATION_FLAGS \ >> + (FEATURE_GT | FEATURE_GA | FEATURE_GIOSUP | \ >> + FEATURE_PPR | FEATURE_EPHSUP) >> + >> +static void _build_efr_guest_translation(struct amd_iommu *iommu, u64 *efr, u64 *efr2) >> +{ >> + /* >> + * Build the EFR against the current hardware capabilities >> + * >> + * Also, not all IOMMU features are emulated by KVM. >> + * Therefore, only advertise what KVM can support >> + * or virtualzied by the hardware. >> + */ > > What does KVM have to do with iommu features on AMD architecture?? Sorry, I meant to say hypervisor. >> + if (!efr) >> + return; >> + >> + *efr |= (amd_iommu_efr & AMD_VIOMMU_EFR_GUEST_TRANSLATION_FLAGS); >> + *efr |= (FIELD_GET(FEATURE_GATS, amd_iommu_efr) << FEATURE_GATS_SHIFT); >> + *efr |= (FIELD_GET(FEATURE_GLX, amd_iommu_efr) << FEATURE_GLX_SHIFT); >> + *efr |= (FIELD_GET(FEATURE_PASMAX, amd_iommu_efr) << FEATURE_PASMAX_SHIFT); >> + pr_debug("%s: efr=%#llx\n", __func__, *efr); >> +} > > I'm not sure all this masking is a good idea, how do you intend to > handshake upgrades when more features are supported if masking is > present? > > Nothing sets efr2? We are planning to extend this function to advertise additional flags in EFR/EFR2 once we add guest support for the corresponded features in the hypervisor in the future. >> +/** >> + * struct iommu_hw_info_amd - AMD IOMMU device info >> + * >> + * @efr : Value of AMD IOMMU Extended Feature Register (EFR) >> + * @efr2: Value of AMD IOMMU Extended Feature 2 Register (EFR2) >> + * >> + * Please See description of these registers in the following sections of >> + * the AMD I/O Virtualization Technology (IOMMU) Specification. >> + * (https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/specifications/48882_IOMMU.pdf) >> + * >> + * - MMIO Offset 0030h IOMMU Extended Feature Register >> + * - MMIO Offset 01A0h IOMMU Extended Feature 2 Register >> + */ > > Need to document the masking and explain what the forwards/backwards > compatible strategy is here. Sure, I can add a note that certain EFR/EFR2 are masked based on the available support in the hypervisor. > I think you should probably just pass the raw HW value through and > require the VMM to figure out what bits it needs based on feature > flags elsewhere. The problem is some of the features are virtualized by hardware, which needs enabling from the Linux AMD IOMMU driver. We cannot just provide all flags since VMM would not know if the kernel has the support enabled. Some of these bits are also propagated to guest AMD IOMMU driver. If we don't mask them, the guest would detect and try to enable unsupported features, which would cause failure. Thanks, Suravee