[PATCH 0/7] x86: tag application address space for devices

Fenghua Yu
2020-03-30T20:38:07Z

Typical hardware devices require a driver stack to translate application
buffers to hardware addresses, and a kernel-user transition to notify the
hardware of new work. What if both the translation and transition overhead
could be eliminated? This is what Shared Virtual Address (SVA) and ENQCMD
enabled hardware like Data Streaming Accelerator (DSA) aims to achieve.
Applications map portals in their local-address-space and directly submit
work to them using a new instruction.

This series implements management of a new MSR (MSR_IA32_PASID). This new
MSR allows an application address space to be associated with what the PCIe
spec calls a Process Address Space ID (PASID). This PASID tag is carried
along with all requests between applications and devices and allows devices
to interact with the process address space.

SVA and ENQCMD enabled device drivers will use this series in the future.
For example, it will be used by the phase 2 DSA driver which will be
released with SVA and ENQCMD support as explained in:
https://01.org/blogs/2019/introducing-intel-data-streaming-accelerator

This series only provides simple and basic support for the MSR as follows:
1. Explain different various technical terms used in the series (patch 1).
2. Enumerate support for ENQCMD in the processor (patch 2).
3. Handle FPU PASID state and the MSR during context switch (patches 3-4).
4. Allocate and free PASID for a process (patch 5).
5. Fix up the PASID MSR in #GP handler when one thread in a process
executes ENQCMD for the first time (patches 6).
6. Clear PASID state for forked and cloned thread (patch 7).

And this patch series needs support from supervisor states patch set:
https://lore.kernel.org/lkml/20200328164307.17497-1-yu-cheng.yu@intel.com/

The v3 supervisor states series, this patch series, and DSA phase 2 series
(to be released shortly in idxd driver) can be cloned from:
https://github.com/intel/idxd-driver.git idxd-stage2

References:
1. Detailed information on the ENQCMD/ENQCMDS instructions and the
IA32_PASID MSR can be found in Intel Architecture Instruction Set
Extensions and Future Features Programming Reference:
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

2. Detailed information on DSA can be found in DSA specification:
https://software.intel.com/en-us/download/intel-data-streaming-accelerator-preliminary-architecture-specification

Ashok Raj (1):
docs: x86: Add a documentation for ENQCMD

Fenghua Yu (5):
x86/cpufeatures: Enumerate ENQCMD and ENQCMDS instructions
x86/msr-index: Define IA32_PASID MSR
x86/mmu: Allocate/free PASID
x86/traps: Fix up invalid PASID
x86/process: Clear PASID state for a newly forked/cloned thread

Yu-cheng Yu (1):
x86/fpu/xstate: Add supervisor PASID state for ENQCMD feature

Documentation/x86/enqcmd.rst | 185 +++++++++++++++++++++++++++++
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/include/asm/fpu/types.h | 10 ++
arch/x86/include/asm/fpu/xstate.h | 2 +-
arch/x86/include/asm/iommu.h | 3 +
arch/x86/include/asm/mmu.h | 4 +
arch/x86/include/asm/mmu_context.h | 14 +++
arch/x86/include/asm/msr-index.h | 3 +
arch/x86/kernel/cpu/cpuid-deps.c | 1 +
arch/x86/kernel/fpu/xstate.c | 4 +
arch/x86/kernel/process.c | 13 ++
arch/x86/kernel/traps.c | 17 +++
drivers/iommu/intel-svm.c | 119 +++++++++++++++++--
13 files changed, 367 insertions(+), 9 deletions(-)
create mode 100644 Documentation/x86/enqcmd.rst

--
2.19.1