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Thu, 25 Mar 2021 17:44:00 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.8.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp1.osuosl.org (Postfix) with ESMTPS id C4DCF82CDE for ; Thu, 25 Mar 2021 17:44:00 +0000 (UTC) Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 47F8D61A1E; Thu, 25 Mar 2021 17:44:00 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94) (envelope-from ) id 1lPU1W-003nbD-6t; Thu, 25 Mar 2021 17:43:58 +0000 Date: Thu, 25 Mar 2021 17:43:57 +0000 Message-ID: <87zgyrqgbm.wl-maz@kernel.org> From: Marc Zyngier To: Megha Dey Subject: Re: [Patch V2 12/13] irqchip: Add IMS (Interrupt Message Store) driver In-Reply-To: <1614370277-23235-13-git-send-email-megha.dey@intel.com> References: <1614370277-23235-1-git-send-email-megha.dey@intel.com> <1614370277-23235-13-git-send-email-megha.dey@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: megha.dey@intel.com, tglx@linutronix.de, linux-kernel@vger.kernel.org, dave.jiang@intel.com, ashok.raj@intel.com, kevin.tian@intel.com, dwmw@amazon.co.uk, x86@kernel.org, tony.luck@intel.com, dan.j.williams@intel.com, jgg@mellanox.com, kvm@vger.kernel.org, iommu@lists.linux-foundation.org, alex.williamson@redhat.com, bhelgaas@google.com, linux-pci@vger.kernel.org, baolu.lu@linux.intel.com, ravi.v.shankar@intel.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Cc: alex.williamson@redhat.com, kevin.tian@intel.com, tony.luck@intel.com, dave.jiang@intel.com, ashok.raj@intel.com, kvm@vger.kernel.org, ravi.v.shankar@intel.com, linux-pci@vger.kernel.org, x86@kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, jgg@mellanox.com, bhelgaas@google.com, tglx@linutronix.de, dan.j.williams@intel.com, dwmw@amazon.co.uk X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Fri, 26 Feb 2021 20:11:16 +0000, Megha Dey wrote: > > Generic IMS(Interrupt Message Store) irq chips and irq domain > implementations for IMS based devices which store the interrupt messages > in an array in device memory. > > Allocation and freeing of interrupts happens via the generic > msi_domain_alloc/free_irqs() interface. No special purpose IMS magic > required as long as the interrupt domain is stored in the underlying > device struct. The irq_set_auxdata() is used to program the pasid into > the IMS entry. > > [Megha: Fixed compile time errors > Added necessary dependencies to IMS_MSI_ARRAY config > Fixed polarity of IMS_VECTOR_CTRL > Added reads after writes to flush writes to device > Added set_desc ops to IMS msi domain ops > Tested the IMS infrastructure with the IDXD driver] > > Reviewed-by: Tony Luck > Signed-off-by: Thomas Gleixner > Signed-off-by: Megha Dey > --- > drivers/irqchip/Kconfig | 14 +++ > drivers/irqchip/Makefile | 1 + > drivers/irqchip/irq-ims-msi.c | 211 ++++++++++++++++++++++++++++++++++++ > include/linux/irqchip/irq-ims-msi.h | 68 ++++++++++++ > 4 files changed, 294 insertions(+) > create mode 100644 drivers/irqchip/irq-ims-msi.c > create mode 100644 include/linux/irqchip/irq-ims-msi.h > > diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig > index e74fa20..2fb0c24 100644 > --- a/drivers/irqchip/Kconfig > +++ b/drivers/irqchip/Kconfig > @@ -586,4 +586,18 @@ config MST_IRQ > help > Support MStar Interrupt Controller. > > +config IMS_MSI > + depends on PCI > + select DEVICE_MSI > + bool > + > +config IMS_MSI_ARRAY > + bool "IMS Interrupt Message Store MSI controller for device memory storage arrays" > + depends on PCI > + select IMS_MSI > + select GENERIC_MSI_IRQ_DOMAIN > + help > + Support for IMS Interrupt Message Store MSI controller > + with IMS slot storage in a slot array in device memory > + > endmenu > diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile > index c59b95a..e903201 100644 > --- a/drivers/irqchip/Makefile > +++ b/drivers/irqchip/Makefile > @@ -113,3 +113,4 @@ obj-$(CONFIG_LOONGSON_PCH_MSI) += irq-loongson-pch-msi.o > obj-$(CONFIG_MST_IRQ) += irq-mst-intc.o > obj-$(CONFIG_SL28CPLD_INTC) += irq-sl28cpld.o > obj-$(CONFIG_MACH_REALTEK_RTL) += irq-realtek-rtl.o > +obj-$(CONFIG_IMS_MSI) += irq-ims-msi.o > diff --git a/drivers/irqchip/irq-ims-msi.c b/drivers/irqchip/irq-ims-msi.c > new file mode 100644 > index 0000000..fa23207 > --- /dev/null > +++ b/drivers/irqchip/irq-ims-msi.c > @@ -0,0 +1,211 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// (C) Copyright 2021 Thomas Gleixner > +/* > + * Shared interrupt chips and irq domains for IMS devices > + */ > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +#ifdef CONFIG_IMS_MSI_ARRAY Given that this covers the whole driver, what is this #defined used for? You might as well make the driver depend on this config option. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu