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bh=6zwh3uv/4dKOUDKuvTiQugEhD9LKpVaA1KJEov11HNA=; b=Gkbq1f940VjEFB7RcelT/nEFEFeob2o+JrG7mJhJehloqfY8ch4uM/Qs+lbGDkESzlBZwu G1rjZoHHvjm5tZRqJn8U+pBTL82HfgcMOvb5Edbx6cyYOGjbib2THgLhLiPlPHaXYSaX/Q Ecl/OAR4iXGUjz6Gw381JYbA8nWwwF4= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-294-leaykoy7M9GUz5dciJ2ADQ-1; Thu, 16 Jul 2020 03:52:00 -0400 X-MC-Unique: leaykoy7M9GUz5dciJ2ADQ-1 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id A915E107BEF5; Thu, 16 Jul 2020 07:51:58 +0000 (UTC) Received: from [10.36.115.54] (ovpn-115-54.ams2.redhat.com [10.36.115.54]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 8F72F2B6D6; Thu, 16 Jul 2020 07:51:56 +0000 (UTC) Subject: Re: [PATCH v4 4/7] iommu/vt-d: Handle non-page aligned address To: Jacob Pan , iommu@lists.linux-foundation.org, LKML , Lu Baolu , Joerg Roedel , David Woodhouse References: <1594080774-33413-1-git-send-email-jacob.jun.pan@linux.intel.com> <1594080774-33413-5-git-send-email-jacob.jun.pan@linux.intel.com> From: Auger Eric Message-ID: <889b3fcd-482a-46b7-7b95-19555f73f907@redhat.com> Date: Thu, 16 Jul 2020 09:51:54 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: <1594080774-33413-5-git-send-email-jacob.jun.pan@linux.intel.com> Content-Language: en-US X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 Cc: "Tian, Kevin" , Raj Ashok X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" Hi Jacob, On 7/7/20 2:12 AM, Jacob Pan wrote: > From: Liu Yi L > > Address information for device TLB invalidation comes from userspace > when device is directly assigned to a guest with vIOMMU support. > VT-d requires page aligned address. This patch checks and enforce > address to be page aligned, otherwise reserved bits can be set in the > invalidation descriptor. Unrecoverable fault will be reported due to > non-zero value in the reserved bits. > > Fixes: 61a06a16e36d8 ("iommu/vt-d: Support flushing more translation > cache types") > Acked-by: Lu Baolu > Signed-off-by: Liu Yi L > Signed-off-by: Jacob Pan Reviewed-by: Eric Auger Thanks Eric > > --- > drivers/iommu/intel/dmar.c | 20 ++++++++++++++++++-- > 1 file changed, 18 insertions(+), 2 deletions(-) > > diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c > index d9f973fa1190..b2c53bada905 100644 > --- a/drivers/iommu/intel/dmar.c > +++ b/drivers/iommu/intel/dmar.c > @@ -1455,9 +1455,25 @@ void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid, > * Max Invs Pending (MIP) is set to 0 for now until we have DIT in > * ECAP. > */ > - desc.qw1 |= addr & ~mask; > - if (size_order) > + if (addr & GENMASK_ULL(size_order + VTD_PAGE_SHIFT, 0)) > + pr_warn_ratelimited("Invalidate non-aligned address %llx, order %d\n", addr, size_order); > + > + /* Take page address */ > + desc.qw1 = QI_DEV_EIOTLB_ADDR(addr); > + > + if (size_order) { > + /* > + * Existing 0s in address below size_order may be the least > + * significant bit, we must set them to 1s to avoid having > + * smaller size than desired. > + */ > + desc.qw1 |= GENMASK_ULL(size_order + VTD_PAGE_SHIFT, > + VTD_PAGE_SHIFT); > + /* Clear size_order bit to indicate size */ > + desc.qw1 &= ~mask; > + /* Set the S bit to indicate flushing more than 1 page */ > desc.qw1 |= QI_DEV_EIOTLB_SIZE; > + } > > qi_submit_sync(iommu, &desc, 1, 0); > } > _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu