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Thu, 29 Jul 2021 04:38:23 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 90FBDC433F1; Thu, 29 Jul 2021 04:38:23 +0000 (UTC) Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: saiprakash.ranjan) by smtp.codeaurora.org (Postfix) with ESMTPSA id 6DFA3C433D3; Thu, 29 Jul 2021 04:38:22 +0000 (UTC) MIME-Version: 1.0 Date: Thu, 29 Jul 2021 10:08:22 +0530 From: Sai Prakash Ranjan To: Georgi Djakov Subject: Re: [PATCH 0/3] iommu/drm/msm: Allow non-coherent masters to use system cache In-Reply-To: <20210728140052.GB22887@mms-0441> References: <20210728140052.GB22887@mms-0441> Message-ID: <8b2742c8891abe4fec3664730717a089@codeaurora.org> X-Sender: saiprakash.ranjan@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 Cc: isaacm@codeaurora.org, David Airlie , Will Deacon , Akhil P Oommen , iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Sean Paul , Jordan Crouse , Kristian H Kristensen , dri-devel@lists.freedesktop.org, Daniel Vetter , linux-arm-msm@vger.kernel.org, freedreno , Robin Murphy , linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" Hi Georgi, On 2021-07-28 19:30, Georgi Djakov wrote: > On Mon, Jan 11, 2021 at 07:45:02PM +0530, Sai Prakash Ranjan wrote: >> commit ecd7274fb4cd ("iommu: Remove unused IOMMU_SYS_CACHE_ONLY flag") >> removed unused IOMMU_SYS_CACHE_ONLY prot flag and along with it went >> the memory type setting required for the non-coherent masters to use >> system cache. Now that system cache support for GPU is added, we will >> need to set the right PTE attribute for GPU buffers to be sys cached. >> Without this, the system cache lines are not allocated for GPU. >> >> So the patches in this series introduces a new prot flag IOMMU_LLC, >> renames IO_PGTABLE_QUIRK_ARM_OUTER_WBWA to IO_PGTABLE_QUIRK_PTW_LLC >> and makes GPU the user of this protection flag. > > Hi Sai, > > Thank you for the patchset! Are you planning to refresh it, as it does > not apply anymore? > I was waiting on Will's reply [1]. If there are no changes needed, then I can repost the patch. [1] https://lore.kernel.org/lkml/21239ba603d0bdc4e4c696588a905f88@codeaurora.org/ Thanks, Sai > >> >> The series slightly depends on following 2 patches posted earlier and >> is based on msm-next branch: >> * https://lore.kernel.org/patchwork/patch/1363008/ >> * https://lore.kernel.org/patchwork/patch/1363010/ >> >> Sai Prakash Ranjan (3): >> iommu/io-pgtable: Rename last-level cache quirk to >> IO_PGTABLE_QUIRK_PTW_LLC >> iommu/io-pgtable-arm: Add IOMMU_LLC page protection flag >> drm/msm: Use IOMMU_LLC page protection flag to map gpu buffers >> >> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 +++ >> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +- >> drivers/gpu/drm/msm/msm_iommu.c | 3 +++ >> drivers/gpu/drm/msm/msm_mmu.h | 4 ++++ >> drivers/iommu/io-pgtable-arm.c | 9 ++++++--- >> include/linux/io-pgtable.h | 6 +++--- >> include/linux/iommu.h | 6 ++++++ >> 7 files changed, 26 insertions(+), 7 deletions(-) >> >> >> base-commit: 00fd44a1a4700718d5d962432b55c09820f7e709 >> -- >> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a >> member >> of Code Aurora Forum, hosted by The Linux Foundation >> -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu