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Fri, 08 Jan 2021 05:47:26 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 70C63C43462; Fri, 8 Jan 2021 05:47:26 +0000 (UTC) Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: saiprakash.ranjan) by smtp.codeaurora.org (Postfix) with ESMTPSA id 6AA3FC433C6; Fri, 8 Jan 2021 05:47:25 +0000 (UTC) MIME-Version: 1.0 Date: Fri, 08 Jan 2021 11:17:25 +0530 From: Sai Prakash Ranjan To: isaacm@codeaurora.org Subject: Re: [PATCH] iommu/io-pgtable-arm: Allow non-coherent masters to use system cache In-Reply-To: References: <20201224064007.2339-1-saiprakash.ranjan@codeaurora.org> <20210106115615.GA1763@willie-the-truck> Message-ID: <8cfefbff135a5287d177b6ab2ccc3304@codeaurora.org> X-Sender: saiprakash.ranjan@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 Cc: linux-arm-msm@vger.kernel.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Akhil P Oommen , Will Deacon , linux-arm-kernel@lists.infradead.org, Robin Murphy X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On 2021-01-07 22:27, isaacm@codeaurora.org wrote: > On 2021-01-06 03:56, Will Deacon wrote: >> On Thu, Dec 24, 2020 at 12:10:07PM +0530, Sai Prakash Ranjan wrote: >>> commit ecd7274fb4cd ("iommu: Remove unused IOMMU_SYS_CACHE_ONLY >>> flag") >>> removed unused IOMMU_SYS_CACHE_ONLY prot flag and along with it went >>> the memory type setting required for the non-coherent masters to use >>> system cache. Now that system cache support for GPU is added, we will >>> need to mark the memory as normal sys-cached for GPU to use system >>> cache. >>> Without this, the system cache lines are not allocated for GPU. We >>> use >>> the IO_PGTABLE_QUIRK_ARM_OUTER_WBWA quirk instead of a page >>> protection >>> flag as the flag cannot be exposed via DMA api because of no in-tree >>> users. >>> >>> Signed-off-by: Sai Prakash Ranjan >>> --- >>> drivers/iommu/io-pgtable-arm.c | 3 +++ >>> 1 file changed, 3 insertions(+) >>> >>> diff --git a/drivers/iommu/io-pgtable-arm.c >>> b/drivers/iommu/io-pgtable-arm.c >>> index 7c9ea9d7874a..3fb7de8304a2 100644 >>> --- a/drivers/iommu/io-pgtable-arm.c >>> +++ b/drivers/iommu/io-pgtable-arm.c >>> @@ -415,6 +415,9 @@ static arm_lpae_iopte arm_lpae_prot_to_pte(struct >>> arm_lpae_io_pgtable *data, >>> else if (prot & IOMMU_CACHE) >>> pte |= (ARM_LPAE_MAIR_ATTR_IDX_CACHE >>> << ARM_LPAE_PTE_ATTRINDX_SHIFT); >>> + else if (data->iop.cfg.quirks & IO_PGTABLE_QUIRK_ARM_OUTER_WBWA) >>> + pte |= (ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE >>> + << ARM_LPAE_PTE_ATTRINDX_SHIFT); >>> } >> > While this approach of enabling system cache globally for both page > tables and other buffers > works for the GPU usecase, this isn't ideal for other clients that use > system cache. For example, > video clients only want to cache a subset of their buffers in the > system cache, due to the sizing constraint > imposed by how much of the system cache they can use. So, it would be > ideal to have > a way of expressing the desire to use the system cache on a per-buffer > basis. Additionally, > our video clients use the DMA layer, and since the requirement is for > caching in the system cache > to be a per buffer attribute, it seems like we would have to have a > DMA attribute to express > this on a per-buffer basis. > I did bring this up initially [1], also where is this video client in upstream? AFAIK, only system cache user in upstream is GPU. We cannot add any DMA attribute unless there is any user upstream as per [2], so when the support for such a client is added, wouldn't ((data->iop.cfg.quirks & IO_PGTABLE_QUIRK_ARM_OUTER_WBWA) || PROT_FLAG) work? [1] https://lore.kernel.org/dri-devel/ecfda7ca80f6d7b4ff3d89b8758f4dc9@codeaurora.org/ [2] https://lore.kernel.org/linux-iommu/20191026053026.GA14545@lst.de/T/ Thanks, Sai -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu