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Tue, 29 Oct 2024 05:09:04 +0000 Message-ID: <91d59b7d-58b0-4da2-af59-18a980273bb4@intel.com> Date: Tue, 29 Oct 2024 13:13:42 +0800 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 2/5] iommu/vt-d: Remove the pasid present check in prq_event_thread To: Baolu Lu , Joel Granados CC: David Woodhouse , Joerg Roedel , Will Deacon , Robin Murphy , "Jason Gunthorpe" , Kevin Tian , Klaus Jensen , , , Klaus Jensen References: <20241015-jag-iopfv8-v4-0-b696ca89ba29@kernel.org> <20241015-jag-iopfv8-v4-2-b696ca89ba29@kernel.org> <90c772ce-6d2d-4a1d-bfec-5a7813be43e4@intel.com> Content-Language: en-US From: Yi Liu In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: SI2PR02CA0032.apcprd02.prod.outlook.com (2603:1096:4:195::12) To DS0PR11MB7529.namprd11.prod.outlook.com (2603:10b6:8:141::20) Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR11MB7529:EE_|BL3PR11MB6361:EE_ X-MS-Office365-Filtering-Correlation-Id: bc7e9efb-b70b-4719-f784-08dcf7d7cebf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|366016|376014|1800799024; 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remove the check >>>> for the pasid present bit in the request. This change was not included >>>> in the creation of prq.c to emphasize the change in capability checks >>>> when handing PRQ events. >>>> >>>> Signed-off-by: Klaus Jensen >>>> Reviewed-by: Kevin Tian >>>> Signed-off-by: Joel Granados >>> looks like the PRQ draining is missed for the PRI usage. When a pasid >>> entry is destroyed, it might need to add helper similar to the >>> intel_drain_pasid_prq() to drain PRQ for the non-pasid usage. >> These types of user space PRIs (non-pasid, non-svm) are created by >> making use of iommufd_hwpt_replace_device. Which adds an entry to the >> pasid_array indexed on IOMMU_NO_PASID (0U) via the following path: >> >> iommufd_hwpt_replace_device >>    -> iommufd_fault_domain_repalce_dev >>      -> __fault_domain_replace_dev >>        -> iommu_replace_group_handle >            -> __iommu_group_set_domain >              -> intel_iommu_attach_device >                 -> device_block_translation >                   -> intel_pasid_tear_down_entry(IOMMU_NO_PASID) > > Here a domain is removed from the pasid entry, hence we need to flush > all page requests that are pending in the IOMMU page request queue or > the PCI fabric. > >>          -> xa_reserve(&group->pasid_array, IOMMU_NO_PASID, GFP_KERNEL); >> >> It is my understanding that this will provide the needed relation >> between the device and the prq in such a way that when  remove_dev_pasid >> is called, intel_iommu_drain_pasid_prq will be called with the >> appropriate pasid value set to IOMMU_NO_PASID. Please correct me if I'm >> mistaken. > > Removing a domain from a RID and a PASID are different paths. > Previously, this IOMMU driver only supported page requests on PASID > (non-IOMMU_NO_PASID). It is acceptable that it does not flush the PRQ in > the domain-removing RID path. > > With the changes made in this series, the driver now supports page > requests for RID. It should also flush the PRQ when removing a domain > from a PASID entry for IOMMU_NO_PASID. > >> >> Does this answer your question? Do you have a specific path that you are >> looking at where a specific non-pasid drain is needed? > > Perhaps we can simply add below change. > > diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c > index e860bc9439a2..a24a42649621 100644 > --- a/drivers/iommu/intel/iommu.c > +++ b/drivers/iommu/intel/iommu.c > @@ -4283,7 +4283,6 @@ static void intel_iommu_remove_dev_pasid(struct > device *dev, ioasid_t pasid, >         intel_iommu_debugfs_remove_dev_pasid(dev_pasid); >         kfree(dev_pasid); >         intel_pasid_tear_down_entry(iommu, dev, pasid, false); > -       intel_drain_pasid_prq(dev, pasid); >  } > >  static int intel_iommu_set_dev_pasid(struct iommu_domain *domain, > diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c > index 2e5fa0a23299..8639f3eb4264 100644 > --- a/drivers/iommu/intel/pasid.c > +++ b/drivers/iommu/intel/pasid.c > @@ -265,6 +265,7 @@ void intel_pasid_tear_down_entry(struct intel_iommu > *iommu, struct device *dev, >                 iommu->flush.flush_iotlb(iommu, did, 0, 0, > DMA_TLB_DSI_FLUSH); > >         devtlb_invalidation_with_pasid(iommu, dev, pasid); > +       intel_drain_pasid_prq(dev, pasid); >  } > >  /* > diff --git a/drivers/iommu/intel/svm.c b/drivers/iommu/intel/svm.c > index 078d1e32a24e..ff88f31053d1 100644 > --- a/drivers/iommu/intel/svm.c > +++ b/drivers/iommu/intel/svm.c > @@ -304,9 +304,6 @@ void intel_drain_pasid_prq(struct device *dev, u32 pasid) >         int qdep; > >         info = dev_iommu_priv_get(dev); > -       if (WARN_ON(!info || !dev_is_pci(dev))) > -               return; > - >         if (!info->pri_enabled) >                 return; > > Generally, intel_drain_pasid_prq() should be called if > > - a translation is removed from a pasid entry; and > - PRI on this device is enabled. If the @pasid==IOMMU_NO_PASID, PRQ drain should use the iotlb invalidation and dev-tlb invalidation descriptors. So extra code change is needed in intel_drain_pasid_prq(). Or perhaps it's better to have a separate helper for draining prq for non-pasid case. -- Regards, Yi Liu