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Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [Patch v1] iommu: arm-smmu: disable large page mappings for Nvidia arm-smmu Content-Language: en-US To: Ashish Mhetre , thierry.reding@gmail.com, vdumpa@nvidia.com, will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org References: <20220417090432.21110-1-amhetre@nvidia.com> In-Reply-To: <20220417090432.21110-1-amhetre@nvidia.com> X-ClientProxiedBy: AM6PR10CA0036.EURPRD10.PROD.OUTLOOK.COM (2603:10a6:209:89::49) To CO6PR12MB5444.namprd12.prod.outlook.com (2603:10b6:5:35e::8) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2078c21c-7740-4fe5-4c9f-08da22034ba4 X-MS-TrafficTypeDiagnostic: DM6PR12MB3180:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: CElxR09K0fh0/Ul5sULHPI9uwtGF2PQDeNgv/PhIembT+63gfTZcqB5RYmRIpMw2L0Z7lsSZEUeUVWo5xDl8Wj5RLsvFUxgZmCIGCCrjZQ64sEsP6+BggHcJcYFb2h6t/O4zt0weBZ8oN3M4adiwAgPiLMvFEn0cJ6TYMOxALKHYfJm0qdc3WwcsfD5q94a13T4CGie/+5Pxlg1wDGkOjN9YTCyxNWhddd+ZPL6p8X4aR9a9E5YLS+57rmT460PWkLo0dcxdTs4D59qw8Plw7Odblb6ANy61+KcWTOR1FGpFyWO8ShwQdoEMxmxl6FDYsavN7tiWK3ZLTrXeHhw+PIKgOgkpSw4ZrvwU6lZJt/SjfH7EkJqf7a/kbz42tTfjn76KYCocy4I+WeKIIfyUIIzxSVutP95N3BIsDGwBC9ePWUcu48+bo5vPrTjG/wf4WcVvyJDN3a+zwkc3Iaw1L4gG5a8VpjYL0abLBqxm8ukEiOmnpFsGznPlTxWi3CZ199mX2E5BuIE3POLc7Z4FNdA/OqWmgnLuF785HXrORFoVEKvG+00vJEQ/DUO+/vfM7G4Oh22D8Ue3bqN3k67wlwUmofEac4JrcsUSlscJ/Fx7vKyEFJByzNuix1dPH3j5rXYJ+2LZ878rzdb7xh3IyHSuAt3xIt8jE2OydZNdkQRHO+Pu8p+cr/omam9ONdrBTt+5YxcUAg+B9ebNxlpirqlcFLOxJhb5zjAdYPvLDh7E1s/C658lu1J4+3frKCVmWDPAl3TnopnWQ4xtkhsF7Q== X-Forefront-Antispam-Report: CIP:255.255.255.255; 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charset="us-ascii"; Format="flowed" Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On 17/04/2022 10:04, Ashish Mhetre wrote: > Tegra194 and Tegra234 SoCs have the erratum that causes walk cache > entries to not be invalidated correctly. The problem is that the walk > cache index generated for IOVA is not same across translation and > invalidation requests. This is leading to page faults when PMD entry is > released during unmap and populated with new PTE table during subsequent > map request. Disabling large page mappings avoids the release of PMD > entry and avoid translations seeing stale PMD entry in walk cache. > Fix this by limiting the page mappings to PAGE_SIZE for Tegra194 and > Tegra234 devices. This is recommended fix from Tegra hardware design > team. > > Co-developed-by: Pritesh Raithatha > Signed-off-by: Pritesh Raithatha > Signed-off-by: Ashish Mhetre > --- > drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c | 23 ++++++++++++++++++++ > drivers/iommu/arm/arm-smmu/arm-smmu.c | 3 +++ > drivers/iommu/arm/arm-smmu/arm-smmu.h | 1 + > 3 files changed, 27 insertions(+) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c b/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c > index 01e9b50b10a1..b7a3d06da2f4 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c > @@ -258,6 +258,27 @@ static void nvidia_smmu_probe_finalize(struct arm_smmu_device *smmu, struct devi > dev_name(dev), err); > } > > +static void nvidia_smmu_cfg_pgsize_bitmap(struct arm_smmu_device *smmu) > +{ > + const struct device_node *np = smmu->dev->of_node; > + > + /* > + * Tegra194 and Tegra234 SoCs have the erratum that causes walk cache > + * entries to not be invalidated correctly. The problem is that the walk > + * cache index generated for IOVA is not same across translation and > + * invalidation requests. This is leading to page faults when PMD entry > + * is released during unmap and populated with new PTE table during > + * subsequent map request. Disabling large page mappings avoids the > + * release of PMD entry and avoid translations seeing stale PMD entry in > + * walk cache. > + * Fix this by limiting the page mappings to PAGE_SIZE on Tegra194 and > + * Tegra234. > + */ > + if (of_device_is_compatible(np, "nvidia,tegra234-smmu") || > + of_device_is_compatible(np, "nvidia,tegra194-smmu")) > + smmu->pgsize_bitmap = PAGE_SIZE; > +} > + > static const struct arm_smmu_impl nvidia_smmu_impl = { > .read_reg = nvidia_smmu_read_reg, > .write_reg = nvidia_smmu_write_reg, > @@ -268,10 +289,12 @@ static const struct arm_smmu_impl nvidia_smmu_impl = { > .global_fault = nvidia_smmu_global_fault, > .context_fault = nvidia_smmu_context_fault, > .probe_finalize = nvidia_smmu_probe_finalize, > + .cfg_pgsize_bitmap = nvidia_smmu_cfg_pgsize_bitmap, > }; > > static const struct arm_smmu_impl nvidia_smmu_single_impl = { > .probe_finalize = nvidia_smmu_probe_finalize, > + .cfg_pgsize_bitmap = nvidia_smmu_cfg_pgsize_bitmap, > }; > > struct arm_smmu_device *nvidia_smmu_impl_init(struct arm_smmu_device *smmu) > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c > index 568cce590ccc..3692a19a588a 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c > @@ -1872,6 +1872,9 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) > if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH64_64K) > smmu->pgsize_bitmap |= SZ_64K | SZ_512M; > > + if (smmu->impl && smmu->impl->cfg_pgsize_bitmap) > + smmu->impl->cfg_pgsize_bitmap(smmu); > + > if (arm_smmu_ops.pgsize_bitmap == -1UL) > arm_smmu_ops.pgsize_bitmap = smmu->pgsize_bitmap; > else > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h > index 2b9b42fb6f30..5d9b03024969 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h > @@ -442,6 +442,7 @@ struct arm_smmu_impl { > void (*write_s2cr)(struct arm_smmu_device *smmu, int idx); > void (*write_sctlr)(struct arm_smmu_device *smmu, int idx, u32 reg); > void (*probe_finalize)(struct arm_smmu_device *smmu, struct device *dev); > + void (*cfg_pgsize_bitmap)(struct arm_smmu_device *smmu); > }; > > #define INVALID_SMENDX -1 Reviewed-by: Jon Hunter Tested-by: Jon Hunter Thanks! Jon -- nvpublic _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu