From: Andy Lutomirski <luto@amacapital.net>
To: Ard Biesheuvel <ardb@kernel.org>
Cc: "Daniel P. Smith" <dpsmith@apertussolutions.com>,
Ross Philipson <ross.philipson@oracle.com>,
linux-kernel@vger.kernel.org, x86@kernel.org,
linux-integrity@vger.kernel.org, linux-doc@vger.kernel.org,
linux-crypto@vger.kernel.org, kexec@lists.infradead.org,
linux-efi@vger.kernel.org, iommu@lists.linux.dev,
dave.hansen@linux.intel.com,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
"H . Peter Anvin" <hpa@zytor.com>,
mjg59@srcf.ucam.org, James.Bottomley@hansenpartnership.com,
peterhuewe@gmx.de, Jarkko Sakkinen <jarkko@kernel.org>,
jgg@ziepe.ca, nivedita@alum.mit.edu,
Herbert Xu <herbert@gondor.apana.org.au>,
davem@davemloft.net, corbet@lwn.net, ebiederm@xmission.com,
dwmw2@infradead.org, baolu.lu@linux.intel.com,
kanth.ghatraju@oracle.com, andrew.cooper3@citrix.com,
trenchboot-devel@googlegroups.com
Subject: Re: [PATCH v15 00/28] x86: Secure Launch support for Intel TXT
Date: Wed, 18 Feb 2026 12:03:27 -0800 [thread overview]
Message-ID: <CALCETrUE8c-dxRWhtHKz_PojwZuWMXJSzOsFQf2vt5LS3ATwpA@mail.gmail.com> (raw)
In-Reply-To: <49d169bf-0ad2-49be-b7d7-fceb9e7f831a@app.fastmail.com>
On Thu, Feb 12, 2026 at 12:40 PM Ard Biesheuvel <ardb@kernel.org> wrote:
>
> On Thu, 12 Feb 2026, at 20:49, Daniel P. Smith wrote:
> > On 2/9/26 09:04, Ard Biesheuvel wrote:
> ...
> >> Surprisingly, even when doing a secure launch, the EFI runtime services still work happily, which means (AIUI) that code that was excluded from the D-RTM TCB is still being executed at ring 0? Doesn't this defeat D-RTM entirely in the case some exploit is hidden in the EFI runtime code? Should we measure the contents of EfiRuntimeServicesCode regions too?
> >
> > Yes, in fact in the early days I specifically stated that we should
> > provide for the ability to measure the RS blocks. Particularly if you
> > are not in an environment where you can isolate the calls to RS from the
> > TCB. While the RS can pose runtime corruption risks, the larger concern
> > is integrating the D-RTM validation of the Intel System Resources
> > Defense (ISRD), aka SMI isolation/SMM Supervisor, provided by the Intel
> > System Security Report (ISSR). Within the ISSR is a list of memory
> > regions which the SMM Policy Shim (SPS) restricts a SMI handler's access
> > when running. This allows a kernel to restrict what access a SMI handler
> > are able to reach, thus allowing them to be removed from the TCB when
> > the appropriate guards are put in place.
> >
> > If you are interested in understanding these further, Satoshi Tanda has
> > probably the best technical explanation without Intel market speak.
> >
> > ISRD: https://tandasat.github.io/blog/2024/02/29/ISRD.html
> > ISSR: https://tandasat.github.io/blog/2024/03/18/ISSR.html
> >
>
> Thanks, I'll take a look at those.
>
> But would it be better to disable the runtime services by default when doing a secure launch? PREEMPT_RT already does the same.
So I have a possible way to disable EFI runtime service without losing
the ability to write EFI vars. We come up with a simple file format
to store deferred EFI var updates and we come up with a place to put
it so that we find it early-ish in boot the next time around. (This
could be done via integration with systemd-boot or shim some other
boot loader or it could actually be part of the kernel.) And then,
instead of writing variables directly, we write them to the deferred
list and then update them on reboot (before TXT launch, etc). [0]
This would be a distincly nontrivial project and would not work for
all configurations.
As a maybe less painful option, we could disable EFI runtime services
but have a root-writable thing in sysfs that (a) turns them back on
but (b) first extends a PCR to say that they're turned back on.
(Or someone could try running runtime services at CPL3...)
[0] I have thought for years that Intel and AMD should do this on
their end, too. Keep the sensitive part of SMI flash entirely locked
after boot and, instead of using magic SMM stuff to validate that
write attempts have the appropriate permissions and signatures, queue
them up as deferred upates and validate the signatures on the next
boot before locking flash.
next prev parent reply other threads:[~2026-02-18 20:03 UTC|newest]
Thread overview: 80+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-15 23:32 [PATCH v15 00/28] x86: Secure Launch support for Intel TXT Ross Philipson
2025-12-15 23:32 ` [PATCH v15 01/28] tpm: Initial step to reorganize TPM public headers Ross Philipson
2026-01-19 23:40 ` Jarkko Sakkinen
2026-01-19 23:52 ` Jarkko Sakkinen
2026-02-01 16:21 ` Daniel P. Smith
2026-02-01 16:20 ` Daniel P. Smith
2026-02-01 22:46 ` Jarkko Sakkinen
2025-12-15 23:32 ` [PATCH v15 02/28] tpm: Move TPM1 specific definitions and functions to new headers Ross Philipson
2026-01-19 23:57 ` Jarkko Sakkinen
2026-02-01 16:23 ` Daniel P. Smith
2026-02-04 17:44 ` ross.philipson
2026-02-08 13:39 ` Jarkko Sakkinen
2025-12-15 23:32 ` [PATCH v15 03/28] tpm: Move TPM2 " Ross Philipson
2025-12-15 23:32 ` [PATCH v15 04/28] tpm: Move TPM common base definitions to new public common header Ross Philipson
2025-12-15 23:32 ` [PATCH v15 05/28] tpm: Move platform specific definitions to the new PTP header Ross Philipson
2025-12-15 23:32 ` [PATCH v15 06/28] tpm: Add TPM buffer support header for standalone reuse Ross Philipson
2025-12-15 23:32 ` [PATCH v15 07/28] tpm: Remove main TPM header from TPM event log header Ross Philipson
2025-12-15 23:32 ` [PATCH v15 08/28] tpm/tpm_tis: Close all localities Ross Philipson
2026-03-29 22:57 ` Josh Snyder
2025-12-15 23:32 ` [PATCH v15 09/28] tpm/tpm_tis: Address positive localities in tpm_tis_request_locality() Ross Philipson
2025-12-15 23:32 ` [PATCH v15 10/28] tpm/tpm_tis: Allow locality to be set to a different value Ross Philipson
2025-12-15 23:32 ` [PATCH v15 11/28] tpm/sysfs: Show locality used by kernel Ross Philipson
2025-12-15 23:33 ` [PATCH v15 12/28] Documentation/x86: Secure Launch kernel documentation Ross Philipson
2025-12-15 23:33 ` [PATCH v15 13/28] x86: Secure Launch Kconfig Ross Philipson
2025-12-16 3:20 ` Randy Dunlap
2025-12-17 18:11 ` ross.philipson
2025-12-15 23:33 ` [PATCH v15 14/28] x86: Secure Launch Resource Table header file Ross Philipson
2025-12-15 23:33 ` [PATCH v15 15/28] x86: Secure Launch main " Ross Philipson
2025-12-15 23:33 ` [PATCH v15 16/28] x86/txt: Intel Trusted eXecution Technology (TXT) definitions Ross Philipson
2025-12-16 22:14 ` Dave Hansen
2025-12-17 18:44 ` ross.philipson
2025-12-18 16:34 ` Dave Hansen
2025-12-18 18:17 ` ross.philipson
2025-12-15 23:33 ` [PATCH v15 17/28] x86: Add early SHA-1 support for Secure Launch early measurements Ross Philipson
2025-12-16 0:21 ` Eric Biggers
2025-12-17 18:10 ` ross.philipson
2025-12-15 23:33 ` [PATCH v15 18/28] x86: Add early SHA-256 " Ross Philipson
2025-12-15 23:33 ` [PATCH v15 19/28] x86/tpm: Early TPM PCR extending driver Ross Philipson
2025-12-16 21:53 ` Dave Hansen
2025-12-17 18:40 ` ross.philipson
2025-12-17 19:06 ` Dave Hansen
2025-12-19 21:26 ` Daniel P. Smith
2026-01-03 20:44 ` Dave Hansen
2026-01-08 16:21 ` Daniel P. Smith
2026-01-20 0:10 ` Jarkko Sakkinen
2025-12-15 23:33 ` [PATCH v15 20/28] x86/msr: Add variable MTRR base/mask and x2apic ID registers Ross Philipson
2025-12-15 23:33 ` [PATCH v15 21/28] x86/boot: Place TXT MLE header in the kernel_info section Ross Philipson
2025-12-15 23:33 ` [PATCH v15 22/28] x86: Secure Launch kernel early boot stub Ross Philipson
2025-12-16 22:32 ` Dave Hansen
2025-12-17 18:47 ` ross.philipson
2025-12-15 23:33 ` [PATCH v15 23/28] x86: Secure Launch kernel late " Ross Philipson
2025-12-15 23:33 ` [PATCH v15 24/28] x86: Secure Launch SMP bringup support Ross Philipson
2025-12-15 23:33 ` [PATCH v15 25/28] kexec: Secure Launch kexec SEXIT support Ross Philipson
2025-12-15 23:33 ` [PATCH v15 26/28] x86/reboot: Secure Launch SEXIT support on reboot paths Ross Philipson
2025-12-15 23:33 ` [PATCH v15 27/28] x86: Secure Launch late initcall platform module Ross Philipson
2025-12-15 23:33 ` [PATCH v15 28/28] x86/efi: EFI stub DRTM launch support for Secure Launch Ross Philipson
2025-12-16 3:46 ` [PATCH v15 00/28] x86: Secure Launch support for Intel TXT Jarkko Sakkinen
2025-12-17 18:15 ` ross.philipson
2025-12-16 22:14 ` Dave Hansen
2026-01-08 16:36 ` Daniel P. Smith
2026-01-08 16:41 ` Dave Hansen
2026-01-08 16:46 ` Daniel P. Smith
2026-02-09 14:04 ` Ard Biesheuvel
2026-02-12 19:49 ` Daniel P. Smith
2026-02-12 19:54 ` Dave Hansen
2026-02-12 20:39 ` Ard Biesheuvel
2026-02-18 17:30 ` Ard Biesheuvel
2026-02-18 18:02 ` ross.philipson
2026-02-26 18:31 ` ross.philipson
2026-02-26 22:33 ` Ard Biesheuvel
2026-02-18 20:03 ` Andy Lutomirski [this message]
2026-02-18 20:29 ` H. Peter Anvin
2026-02-18 20:34 ` Andy Lutomirski
2026-02-18 21:04 ` Simo Sorce
2026-02-18 21:54 ` Andy Lutomirski
2026-02-19 7:54 ` Ard Biesheuvel
2026-02-19 17:10 ` H. Peter Anvin
2026-02-19 17:34 ` Andy Lutomirski
2026-02-20 8:30 ` Ard Biesheuvel
2026-02-23 21:37 ` Daniel P. Smith
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