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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae35363b35dsm137152566b.13.2025.06.27.07.44.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 27 Jun 2025 07:44:55 -0700 (PDT) Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Fri, 27 Jun 2025 16:44:54 +0200 Message-Id: Cc: <~postmarketos/upstreaming@lists.sr.ht>, , , , , , , , , , Subject: Re: [PATCH 14/14] arm64: dts: qcom: Add The Fairphone (Gen. 6) From: "Luca Weiss" To: "Konrad Dybcio" , "Will Deacon" , "Robin Murphy" , "Joerg Roedel" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Rafael J. Wysocki" , "Viresh Kumar" , "Manivannan Sadhasivam" , "Herbert Xu" , "David S. Miller" , "Vinod Koul" , "Bjorn Andersson" , "Konrad Dybcio" , "Robert Marko" , "Das Srinagesh" , "Thomas Gleixner" , "Jassi Brar" , "Amit Kucheria" , "Thara Gopinath" , "Daniel Lezcano" , "Zhang Rui" , "Lukasz Luba" , "Ulf Hansson" X-Mailer: aerc 0.20.1-0-g2ecb8770224a-dirty References: <20250625-sm7635-fp6-initial-v1-0-d9cd322eac1b@fairphone.com> <20250625-sm7635-fp6-initial-v1-14-d9cd322eac1b@fairphone.com> <4200b3b8-5669-4d5a-a509-d23f921b0449@oss.qualcomm.com> <6d4e77b3-0f92-44dd-b9b0-3129a5f3785b@oss.qualcomm.com> In-Reply-To: <6d4e77b3-0f92-44dd-b9b0-3129a5f3785b@oss.qualcomm.com> On Fri Jun 27, 2025 at 4:34 PM CEST, Konrad Dybcio wrote: > On 6/27/25 1:33 PM, Luca Weiss wrote: >> On Wed Jun 25, 2025 at 4:38 PM CEST, Konrad Dybcio wrote: >>> On 6/25/25 11:23 AM, Luca Weiss wrote: >>>> Add a devicetree for The Fairphone (Gen. 6) smartphone, which is based >>>> on the SM7635 SoC. >>> >>> [...] >>> >>>> + /* Dummy panel for simple-framebuffer dimension info */ >>>> + panel: panel { >>>> + compatible =3D "boe,bj631jhm-t71-d900"; >>>> + width-mm =3D <65>; >>>> + height-mm =3D <146>; >>>> + }; >>> >>> I haven't ran through all the prerequisite-xx-id, but have >>> you submitted a binding for this? >>=20 >> Actually not, kind of forgot about this. I believe I can create a >> (mostly?) complete binding for the panel, but this simple description >> for only width-mm & height-mm will differ from the final one, which will >> have the DSI port, pinctrl, reset-gpios and various supplies. >>=20 >> I think I'll just drop it from v2 and keep it locally only, to get the >> simpledrm scaling right. > > Yeah I think that'd be best in general Ack > >>=20 >>> >>> [...] >>> >>>> + reserved-memory { >>>> + /* >>>> + * ABL is powering down display and controller if this node is >>>> + * not named exactly "splash_region". >>>> + */ >>>> + splash_region@e3940000 { >>>> + reg =3D <0x0 0xe3940000 0x0 0x2b00000>; >>>> + no-map; >>>> + }; >>>> + }; >>> >>> :/ maybe we can convince ABL not to do it.. >>=20 >> Yes, we talked about that. I will look into getting "splash-region" and >> "splash" also into the ABL (edk2) build for the phone. Still won't >> resolve that for any other brand of devices. > > Gotta start small! Maybe framebuffer@ would be more """idiomatic""" > but potayto/potahto I'll try and work on the edk2 patch early next week, so if you tell me soon, I can add some other name. I don't want to include 500 different names though. :) > >>=20 >>> >>> [...] >>> >>>> + vreg_l12b: ldo12 { >>>> + regulator-name =3D "vreg_l12b"; >>>> + /* >>>> + * Skip voltage voting for UFS VCC. >>>> + */ >>> >>> Why so? >>=20 >> From downstream: >>=20 >> /* >> * This is for UFS Peripheral,which supports 2 variants >> * UFS 3.1 ,and UFS 2.2 both require different voltages. >> * Hence preventing voltage voting as per previous targets. >> */ >>=20 >> I haven't (successfully) brought up UFS yet, so I haven't looked more >> into that. >>=20 >> The storage on FP6 is UFS 3.1 though fwiw. > > Hm.. can you check what debugfs says about the voltage at runtime > (on downstream)? I'd assume you won't be shipping two kinds anyway This is very likely just from Qualcomm's baseline. > > [...] > >>>> +&pm8550vs_d { >>>> + status =3D "disabled"; >>>> +}; >>>> + >>>> +&pm8550vs_e { >>>> + status =3D "disabled"; >>>> +}; >>>> + >>>> +&pm8550vs_g { >>>> + status =3D "disabled"; >>>> +}; >>> >>> Hm... perhaps we should disable these by deafult >>=20 >> Do you want me to do this in this patchset, or we clean this up later at >> some point? I'd prefer not adding even more dependencies to my patch >> collection right now. > > I can totally hear that.. > > Let's include it in this patchset, right before SoC addition > I don't think there's any pm8550vs users trying to get merged in > parallel so it should be OK Okay, can do. Disable all of them (_c, _d, _e, _g), and re-enable them in current users? I assume there might also be boards that only have e.g. _d and no _c. > > [...] > >>>> +&usb_1 { >>>> + dr_mode =3D "otg"; >>>> + >>>> + /* USB 2.0 only */ >>> >>> Because there's no usb3phy description yet, or due to hw design? >>=20 >> HW design. Funnily enough with clk_ignore_unused this property is not >> needed, and USB(2.0) works fine then. Just when (I assume) the USB3 >> clock is turned off which the bootloader has enabled, USB stops working. > > The USB controller has two possible clock sources: the PIPE_CLK that > the QMPPHY outputs, or the UTMI clock (qcom,select-utmi-as-pipe-clk). So okay like this for you, for a USB2.0-only HW? > > Because you said there's no USB3, I'm assuming DP-over-Type-C won't > be a thing either? :( Yep. I'd have preferred USB3+DP as well since it's actually quite cool to have with proper Linux. On Android, at least on older versions it's barely usable imo. Can't even properly watch videos on the big screen with that SW stack. Regards Luca > > Konrad