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[83.97.14.181]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afe9c908431sm11361366b.92.2025.08.25.09.40.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 25 Aug 2025 09:40:42 -0700 (PDT) Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Mon, 25 Aug 2025 18:40:41 +0200 Message-Id: Subject: Re: [PATCH v2 14/15] arm64: dts: qcom: Add initial Milos dtsi From: "Luca Weiss" To: "Dmitry Baryshkov" Cc: "Konrad Dybcio" , "Will Deacon" , "Robin Murphy" , "Joerg Roedel" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Rafael J. Wysocki" , "Viresh Kumar" , "Manivannan Sadhasivam" , "Herbert Xu" , "David S. Miller" , "Vinod Koul" , "Bjorn Andersson" , "Konrad Dybcio" , "Robert Marko" , "Das Srinagesh" , "Thomas Gleixner" , "Jassi Brar" , "Amit Kucheria" , "Thara Gopinath" , "Daniel Lezcano" , "Zhang Rui" , "Lukasz Luba" , "Ulf Hansson" , <~postmarketos/upstreaming@lists.sr.ht>, , , , , , , , , , X-Mailer: aerc 0.20.1-0-g2ecb8770224a-dirty References: <20250713-sm7635-fp6-initial-v2-0-e8f9a789505b@fairphone.com> <20250713-sm7635-fp6-initial-v2-14-e8f9a789505b@fairphone.com> <3e0299ad-766a-4876-912e-438fe2cc856d@oss.qualcomm.com> <55420d89-fcd4-4cb5-a918-d8bbe2a03d19@oss.qualcomm.com> <2hv4yuc7rgtglihc2um2lr5ix4dfqxd4abb2bqb445zkhpjpsi@rozikfwrdtlk> <2bk7s43nrkmhhgsqq65mxhbmrapyjejyjugnae7wfbttqjmtbf@dk2fe64qrmwx> In-Reply-To: <2bk7s43nrkmhhgsqq65mxhbmrapyjejyjugnae7wfbttqjmtbf@dk2fe64qrmwx> On Mon Aug 25, 2025 at 6:36 PM CEST, Dmitry Baryshkov wrote: > On Mon, Aug 25, 2025 at 05:53:53PM +0200, Luca Weiss wrote: >> Hi Dmitry, >>=20 >> On Wed Aug 20, 2025 at 1:52 PM CEST, Dmitry Baryshkov wrote: >> > On Wed, Aug 20, 2025 at 10:42:09AM +0200, Luca Weiss wrote: >> >> Hi Konrad, >> >>=20 >> >> On Sat Aug 2, 2025 at 2:04 PM CEST, Konrad Dybcio wrote: >> >> > On 7/29/25 8:49 AM, Luca Weiss wrote: >> >> >> Hi Konrad, >> >> >>=20 >> >> >> On Thu Jul 17, 2025 at 11:46 AM CEST, Luca Weiss wrote: >> >> >>> Hi Konrad, >> >> >>> >> >> >>> On Thu Jul 17, 2025 at 10:29 AM CEST, Luca Weiss wrote: >> >> >>>> On Mon Jul 14, 2025 at 1:06 PM CEST, Konrad Dybcio wrote: >> >> >>>>> On 7/13/25 10:05 AM, Luca Weiss wrote: >> >> >>>>>> Add a devicetree description for the Milos SoC, which is for e= xample >> >> >>>>>> Snapdragon 7s Gen 3 (SM7635). >> >> >>>>>> >> >> >>>>>> Signed-off-by: Luca Weiss >> >> >>>>>> --- >> >> >>>>> >> >> >>>>> [...] >> >> >>>>>> + >> >> >>>>>> + spmi_bus: spmi@c400000 { >> >> >>>>>> + compatible =3D "qcom,spmi-pmic-arb"; >> >> >>>>> >> >> >>>>> There's two bus instances on this platform, check out the x1e b= inding >> >> >>>> >> >> >>>> Will do >> >> >>> >> >> >>> One problem: If we make the labels spmi_bus0 and spmi_bus1 then w= e can't >> >> >>> reuse the existing PMIC dtsi files since they all reference &spmi= _bus. >> >> >>> >> >> >>> On FP6 everything's connected to PMIC_SPMI0_*, and PMIC_SPMI1_* i= s not >> >> >>> connected to anything so just adding the label spmi_bus on spmi_b= us0 >> >> >>> would be fine. >> >> >>> >> >> >>> Can I add this to the device dts? Not going to be pretty though..= . >> >> >>> >> >> >>> diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/a= rch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts >> >> >>> index d12eaa585b31..69605c9ed344 100644 >> >> >>> --- a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts >> >> >>> +++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts >> >> >>> @@ -11,6 +11,9 @@ >> >> >>> #include >> >> >>> #include >> >> >>> #include "milos.dtsi" >> >> >>> + >> >> >>> +spmi_bus: &spmi_bus0 {}; >> >> >>> + >> >> >>> #include "pm7550.dtsi" >> >> >>> #include "pm8550vs.dtsi" >> >> >>> #include "pmiv0104.dtsi" /* PMIV0108 */ >> >> >>> >> >> >>> Or I can add a second label for the spmi_bus0 as 'spmi_bus'. Not = sure >> >> >>> other designs than SM7635 recommend using spmi_bus1 for some stuf= f. >> >> >>> >> >> >>> But I guess longer term we'd need to figure out a solution to thi= s, how >> >> >>> to place a PMIC on a given SPMI bus, if reference designs start t= o >> >> >>> recommend putting different PMIC on the separate busses. >> >> >>=20 >> >> >> Any feedback on this regarding the spmi_bus label? >> >> > >> >> > I had an offline chat with Bjorn and we only came up with janky >> >> > solutions :) >> >> > >> >> > What you propose works well if the PMICs are all on bus0, which is >> >> > not the case for the newest platforms. If some instances are on bus= 0 >> >> > and others are on bus1, things get ugly really quick and we're goin= g >> >> > to drown in #ifdefs. >> >> > >> >> > >> >> > An alternative that I've seen downstream is to define PMIC nodes in >> >> > the root of a dtsi file (not in the root of DT, i.e. NOT under / { = }) >> >> > and do the following: >> >> > >> >> > &spmi_busN { >> >> > #include "pmABCDX.dtsi" >> >> > }; >> >> > >> >> > Which is "okay", but has the visible downside of having to define t= he >> >> > temp alarm thermal zone in each board's DT separately (and doing >> >> > mid-file includes which is.. fine I guess, but also something we av= oided >> >> > upstream for the longest time) >> >> > >> >> > >> >> > Both are less than ideal when it comes to altering the SID under >> >> > "interrupts", fixing that would help immensely. We were hoping to >> >> > leverage something like Johan's work on drivers/mfd/qcom-pm8008.c, >> >> > but that seems like a longer term project. >> >> > >> >> > Please voice your opinions >> >>=20 >> >> Since nobody else jumped in, how can we continue? >> >>=20 >> >> One janky solution in my mind is somewhat similar to the PMxxxx_SID >> >> defines, doing something like "#define PM7550_SPMI spmi_bus0" and the= n >> >> using "&PM7550_SPMI {}" in the dtsi. I didn't try it so not sure that >> >> actually works but something like this should I imagine. >> >>=20 >> >> But fortunately my Milos device doesn't have the problem that it >> >> actually uses both SPMI busses for different PMICs, so similar to oth= er >> >> SoCs that already have two SPMI busses, I could somewhat ignore the >> >> problem and let someone else figure out how to actually place PMICs o= n >> >> spmi_bus0 and spmi_bus1 if they have such a hardware. >> > >> > I'd say, ignore it for now. >>=20 >> You mean ignoring that there's a second SPMI bus on this SoC, and just >> modelling one with the label "spmi_bus"? Or something else? >>=20 >>=20 >> I have also actually tried out the C define solution that I was writing >> about in my previous email and this is actually working, see diff below. >> In my opinion it just expands on what we have with the SID defines, so >> shouldn't be tooo unacceptable :) > > I think we tried previously using C preprocessor to rework SID handling > and it wasn't accepted by DT maintainers. I don't know anything about that, but yeah... > > I'd say, ignore the second bus for now, unless it gets actually used for > major PMICs. The only 'problem' with this is once we do figure out a solution, the SoC bindings will change, so both dt-bindings and dtsi needs to be updated. But that's the case also for sm8550 and friends that currently ignore the second SPMI bus upstream. On FP6 again, it's definitely not a problem since everything's just on the first SPMI bus anyways. So then I'll revert the change to compatible =3D "qcom,milos-spmi-pmic-arb"= , "qcom,x1e80100-spmi-pmic-arb"; plus associated subnodes for the next revision. Regards Luca