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Fri, 26 Mar 2021 09:34:51 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id sb4sm4093833ejb.71.2021.03.26.09.34.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Mar 2021 09:34:49 -0700 (PDT) Date: Fri, 26 Mar 2021 17:35:12 +0100 From: Thierry Reding To: Dmitry Osipenko Subject: Re: [PATCH 0/9] arm64: tegra: Prevent early SMMU faults Message-ID: References: <20210325130332.778208-1-thierry.reding@gmail.com> <197876d1-0046-f673-5d3e-818d1002542b@gmail.com> MIME-Version: 1.0 In-Reply-To: <197876d1-0046-f673-5d3e-818d1002542b@gmail.com> User-Agent: Mutt/2.0.6 (98f8cb83) (2021-03-06) Cc: Krzysztof Kozlowski , Will Deacon , Jon Hunter , iommu@lists.linux-foundation.org, Nicolin Chen , linux-tegra@vger.kernel.org, Robin Murphy , linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============8827677929120950167==" Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" --===============8827677929120950167== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="E3RehJV1Q5CrEkmM" Content-Disposition: inline --E3RehJV1Q5CrEkmM Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Mar 26, 2021 at 06:29:28PM +0300, Dmitry Osipenko wrote: > 25.03.2021 16:03, Thierry Reding =D0=BF=D0=B8=D1=88=D0=B5=D1=82: > > From: Thierry Reding > >=20 > > Hi, > >=20 > > this is a set of patches that is the result of earlier discussions > > regarding early identity mappings that are needed to avoid SMMU faults > > during early boot. > >=20 > > The goal here is to avoid early identity mappings altogether and instead > > postpone the need for the identity mappings to when devices are attached > > to the SMMU. This works by making the SMMU driver coordinate with the > > memory controller driver on when to start enforcing SMMU translations. > > This makes Tegra behave in a more standard way and pushes the code to > > deal with the Tegra-specific programming into the NVIDIA SMMU > > implementation. >=20 > It is an interesting idea which inspired me to try to apply a somewhat si= milar thing to Tegra SMMU driver by holding the SMMU ASID enable-bit until = display driver allows to toggle it. This means that we will need an extra s= mall tegra-specific SMMU API function, but it should be okay. >=20 > I typed a patch and seems it's working good, I'll prepare a proper patch = if you like it. That would actually be working around the problem that this patch was supposed to prepare for. The reason for this current patch series is to make sure SMMU translation isn't enabled until a device has actually been attached to the SMMU. Once it has been attached, the assumption is that any identity mappings will have been created. One Tegra SMMU that shouldn't be a problem because translations aren't enabled until device attach time. So in other words this patch set is to get Tegra186 and later to parity with earlier chips from this point of view. I think the problem that you're trying to work around is better solved by establishing these identity mappings. I do have patches to implement this for Tegra210 and earlier, though they may require additional work if you have bootloaders that don't use standard DT bindings for passing information about the framebuffer to the kernel. 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