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Thu, 25 Mar 2021 08:52:01 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id l15sm8058477wru.38.2021.03.25.08.51.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Mar 2021 08:52:00 -0700 (PDT) Date: Thu, 25 Mar 2021 16:52:22 +0100 From: Thierry Reding To: Dmitry Osipenko Subject: Re: [PATCH 1/9] memory: tegra: Move internal data structures into separate header Message-ID: References: <20210325130332.778208-1-thierry.reding@gmail.com> <20210325130332.778208-2-thierry.reding@gmail.com> MIME-Version: 1.0 In-Reply-To: User-Agent: Mutt/2.0.6 (98f8cb83) (2021-03-06) Cc: Krzysztof Kozlowski , Will Deacon , Jon Hunter , iommu@lists.linux-foundation.org, Nicolin Chen , linux-tegra@vger.kernel.org, Robin Murphy , linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============1071945312005733619==" Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" --===============1071945312005733619== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="3koIXHrG9oTo3ihE" Content-Disposition: inline --3koIXHrG9oTo3ihE Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Mar 25, 2021 at 06:12:51PM +0300, Dmitry Osipenko wrote: > 25.03.2021 16:03, Thierry Reding =D0=BF=D0=B8=D1=88=D0=B5=D1=82: > > From: Thierry Reding > >=20 > > From Tegra20 through Tegra210, either the GART or SMMU drivers need > > access to the internals of the memory controller driver because they are > > tightly coupled (in fact, the GART and SMMU are part of the memory > > controller). On later chips, a separate hardware block implements the > > SMMU functionality, so this is no longer needed. However, we still want > > to reuse some of the existing infrastructure on later chips, so split > > the memory controller internals into a separate header file to avoid > > conflicts with the implementation on newer chips. > >=20 > > Signed-off-by: Thierry Reding > > --- > > drivers/iommu/tegra-gart.c | 2 +- > > drivers/iommu/tegra-smmu.c | 2 +- > > drivers/memory/tegra/mc.h | 2 +- > > drivers/memory/tegra/tegra186.c | 12 ++++--- > > include/soc/tegra/mc-internal.h | 62 +++++++++++++++++++++++++++++++++ > > include/soc/tegra/mc.h | 50 -------------------------- > > 6 files changed, 72 insertions(+), 58 deletions(-) > > create mode 100644 include/soc/tegra/mc-internal.h >=20 > What about to make T186 to re-use the existing tegra_mc struct? Seems > there is nothing special in that struct which doesn't fit for the newer > SoCs. Please notice that both SMMU and GART are already optional and all > the SoC differences are specified within the tegra_mc_soc. It looks to > me that this could be a much nicer and cleaner variant. The problem is that much of the interesting bits in tegra_mc_soc are basically incompatible between the two. For instance the tegra_mc_client and tegra186_mc_client structures, while they have the same purpose, have completely different content. I didn't see a way to unify that without overly complicating things by making half of the fields basically optional on one or the other SoC generation. Maybe one option would be to split tegra_mc into a tegra_mc_common and then derive tegra_mc and tegra186_mc from that. That way we could share the common bits while still letting the chip-specific differences be handled separately. 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