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Received: from j217100.upc-j.chello.nl ([24.132.217.100] helo=noisy.programming.kicks-ass.net) by casper.infradead.org with esmtpsa (Exim 4.94 #2 (Red Hat Linux)) id 1leHDA-000LSn-UF; Wed, 05 May 2021 13:05:20 +0000 Received: from hirez.programming.kicks-ass.net (hirez.programming.kicks-ass.net [192.168.1.225]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (Client did not present a certificate) by noisy.programming.kicks-ass.net (Postfix) with ESMTPS id 2CD993001CD; Wed, 5 May 2021 15:05:06 +0200 (CEST) Received: by hirez.programming.kicks-ass.net (Postfix, from userid 1000) id 2E32A203E67C5; Wed, 5 May 2021 15:05:06 +0200 (CEST) Date: Wed, 5 May 2021 15:05:06 +0200 From: Peter Zijlstra To: "Suthikulpanit, Suravee" Subject: Re: [PATCH] x86/events/amd/iommu: Fix invalid Perf result due to IOMMU PMC power-gating Message-ID: References: <20210504065236.4415-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Cc: David Coe , amonakov@ispras.ru, Jon.Grimm@amd.com, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, iommu@lists.linux-foundation.org, mingo@redhat.com X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Wed, May 05, 2021 at 07:39:14PM +0700, Suthikulpanit, Suravee wrote: > Peter, > > On 5/4/2021 7:13 PM, Peter Zijlstra wrote: > > On Tue, May 04, 2021 at 06:58:29PM +0700, Suthikulpanit, Suravee wrote: > > > Peter, > > > > > > On 5/4/2021 4:39 PM, Peter Zijlstra wrote: > > > > On Tue, May 04, 2021 at 01:52:36AM -0500, Suravee Suthikulpanit wrote: > > > > > > > > > 2. Since AMD IOMMU PMU does not support interrupt mode, the logic > > > > > can be simplified to always start counting with value zero, > > > > > and accumulate the counter value when stopping without the need > > > > > to keep track and reprogram the counter with the previously read > > > > > counter value. > > > > > > > > This relies on the hardware counter being the full 64bit wide, is it? > > > > > > > > > > The HW counter value is 48-bit. Not sure why it needs to be 64-bit? > > > I might be missing some points here? Could you please describe? > > > > How do you deal with the 48bit overflow if you don't use the interrupt? > > The IOMMU Perf driver does not currently handle counter overflow since the overflow > notification mechanism (i.e. IOMMU creates an EVENT_COUNTER_ZERO event in the IOMMU event log, > and generate an IOMMU MSI interrupt to signal IOMMU driver to process the event.) is not > currently supported. When counter overflows, the counter becomes zero, and Perf > reports value zero for the event. > > Alternatively, to detect overflow, we might start counting with value 1 so that > we can detect overflow when the value becomes zero in which case the Perf driver > could generate error message. Urgh.. the intel uncore driver programs an hrtimer to periodically fold deltas. That way the counter will never be short. _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu