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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id c16sm6822645oiw.31.2021.11.08.09.55.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Nov 2021 09:55:42 -0800 (PST) Date: Mon, 8 Nov 2021 09:57:19 -0800 From: Bjorn Andersson To: Rob Clark Subject: Re: [PATCH] iommu/arm-smmu-qcom: Fix TTBR0 read Message-ID: References: <20211108171724.470973-1-robdclark@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20211108171724.470973-1-robdclark@gmail.com> Cc: Rob Clark , Sai Prakash Ranjan , open list , Will Deacon , linux-arm-msm@vger.kernel.org, Robin Murphy , dri-devel@lists.freedesktop.org, Eric Anholt , iommu@lists.linux-foundation.org, Shawn Guo , freedreno@lists.freedesktop.org, "moderated list:ARM SMMU DRIVERS" X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Mon 08 Nov 09:17 PST 2021, Rob Clark wrote: > From: Rob Clark > > It is a 64b register, lets not lose the upper bits. > > Fixes: ab5df7b953d8 ("iommu/arm-smmu-qcom: Add an adreno-smmu-priv callback to get pagefault info") > Signed-off-by: Rob Clark Reviewed-by: Bjorn Andersson Regards, Bjorn > --- > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > index 55690af1b25d..c998960495b4 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > @@ -51,7 +51,7 @@ static void qcom_adreno_smmu_get_fault_info(const void *cookie, > info->fsynr1 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR1); > info->far = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_FAR); > info->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx)); > - info->ttbr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0); > + info->ttbr0 = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0); > info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR); > } > > -- > 2.31.1 > _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu