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[66.90.148.213]) by smtp.gmail.com with ESMTPSA id v19sm2817356ott.13.2021.11.29.13.03.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Nov 2021 13:03:25 -0800 (PST) Received: (nullmailer pid 604956 invoked by uid 1000); Mon, 29 Nov 2021 21:03:24 -0000 Date: Mon, 29 Nov 2021 15:03:24 -0600 From: Rob Herring To: Thierry Reding Subject: Re: [PATCH 1/4] dt-bindings: arm-smmu: Document nvidia,memory-controller property Message-ID: References: <20211112131231.3683098-1-thierry.reding@gmail.com> <20211112131231.3683098-2-thierry.reding@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20211112131231.3683098-2-thierry.reding@gmail.com> Cc: devicetree@vger.kernel.org, Will Deacon , Jon Hunter , iommu@lists.linux-foundation.org, linux-tegra@vger.kernel.org, Robin Murphy , linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Fri, Nov 12, 2021 at 02:12:28PM +0100, Thierry Reding wrote: > From: Thierry Reding > > On NVIDIA SoC's the ARM SMMU needs to interact with the memory > controller in order to map memory clients to the corresponding stream > IDs. Document how the nvidia,memory-controller property can be used to > achieve this. > > Signed-off-by: Thierry Reding > --- > Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > index f66a3effba73..cf32a7955475 100644 > --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > @@ -155,6 +155,12 @@ properties: > power-domains: > maxItems: 1 > > + nvidia,memory-controller: > + description: A phandle to the memory controller on NVIDIA Tegra186 > + and later SoCs. The memory controller needs to be programmed with > + a mapping of memory client IDs to ARM SMMU stream IDs. > + $ref: /schemas/types.yaml#/definitions/phandle > + > required: > - compatible > - reg > @@ -177,6 +183,9 @@ allOf: > reg: > minItems: 1 > maxItems: 2 > + > + required: > + - nvidia,memory-controller That's not a compatible change. Document why it is necessary if that's intended. > else: > properties: > reg: > -- > 2.33.1 > > _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu