From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp3.osuosl.org (smtp3.osuosl.org [140.211.166.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E6DA2C433EF for ; Fri, 13 May 2022 13:07:55 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by smtp3.osuosl.org (Postfix) with ESMTP id 9FB0960EA8; Fri, 13 May 2022 13:07:55 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from smtp3.osuosl.org ([127.0.0.1]) by localhost (smtp3.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ZOmfI-x5WpQP; Fri, 13 May 2022 13:07:51 +0000 (UTC) Received: from lists.linuxfoundation.org (lf-lists.osuosl.org [140.211.9.56]) by smtp3.osuosl.org (Postfix) with ESMTPS id 5AB8460E94; Fri, 13 May 2022 13:07:50 +0000 (UTC) Received: from lf-lists.osuosl.org (localhost [127.0.0.1]) by lists.linuxfoundation.org (Postfix) with ESMTP id 3547BC0032; Fri, 13 May 2022 13:07:50 +0000 (UTC) Received: from smtp2.osuosl.org (smtp2.osuosl.org [IPv6:2605:bc80:3010::133]) by lists.linuxfoundation.org (Postfix) with ESMTP id 815BCC002D for ; Fri, 13 May 2022 13:07:49 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by smtp2.osuosl.org (Postfix) with ESMTP id 6F9A5404EE for ; Fri, 13 May 2022 13:07:49 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from smtp2.osuosl.org ([127.0.0.1]) by localhost (smtp2.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id dp1cRWq8hyfC for ; Fri, 13 May 2022 13:07:49 +0000 (UTC) X-Greylist: from auto-whitelisted by SQLgrey-1.8.0 Received: from theia.8bytes.org (8bytes.org [81.169.241.247]) by smtp2.osuosl.org (Postfix) with ESMTPS id CC7DE4011C for ; Fri, 13 May 2022 13:07:48 +0000 (UTC) Received: by theia.8bytes.org (Postfix, from userid 1000) id E597D4D2; Fri, 13 May 2022 15:07:46 +0200 (CEST) Date: Fri, 13 May 2022 15:07:45 +0200 From: Joerg Roedel To: Suravee Suthikulpanit Subject: Re: [PATCH v2] iommu/amd: Set translation valid bit only when IO page tables are in used Message-ID: References: <20220509074815.11881-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220509074815.11881-1-suravee.suthikulpanit@amd.com> Cc: iommu@lists.linux-foundation.org, jon.grimm@amd.com, linux-kernel@vger.kernel.org, vasant.hegde@amd.com X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Mon, May 09, 2022 at 02:48:15AM -0500, Suravee Suthikulpanit wrote: > On AMD system with SNP enabled, IOMMU hardware checks the host translation > valid (TV) and guest translation valid (GV) bits in the device > table entry (DTE) before accessing the corresponded page tables. > > However, current IOMMU driver sets the TV bit for all devices > regardless of whether the host page table is in used. > This results in ILLEGAL_DEV_TABLE_ENTRY event for devices, which > do not the host page table root pointer set up. Hmm, this sound weird. In the early AMD IOMMUs it was recommended to set TV=1 and V=1 and the rest to 0 to block all DMA from a device. I wonder how this triggers ILLEGAL_DEV_TABLE_ENTRY errors now. It is (was?) legal to set V=1 TV=1, mode=0 and leave the page-table empty. When then IW=0 and IR=0, DMA is blocked. From what I remember this is a valid setting in a DTE. Do you have an example DTE which triggers this error message? Regards, Joerg _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu