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From: Joerg Roedel <joro@8bytes.org>
To: Vasant Hegde <vasant.hegde@amd.com>
Cc: iommu@lists.linux.dev, suravee.suthikulpanit@amd.com
Subject: Re: [PATCH] iommu/amd: Fix DTE_IRQ_PHYS_ADDR_MASK macro
Date: Fri, 16 Jun 2023 16:31:22 +0200	[thread overview]
Message-ID: <ZIxyOohwBv6Bkb0w@8bytes.org> (raw)
In-Reply-To: <20230609090327.5923-1-vasant.hegde@amd.com>

On Fri, Jun 09, 2023 at 09:03:27AM +0000, Vasant Hegde wrote:
> Interrupt Table Root Pointer is 52 bit and table must be aligned to start
> on a 128-byte boundary. Hence first 6 bits are ignored.
> 
> Current code uses address mask as 45 instead of 46bit. Use GENMASK_ULL
> macro instead of manually generating address mask.
> 
> Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
> ---
>  drivers/iommu/amd/amd_iommu_types.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Applied, thanks.

      parent reply	other threads:[~2023-06-16 14:39 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-09  9:03 [PATCH] iommu/amd: Fix DTE_IRQ_PHYS_ADDR_MASK macro Vasant Hegde
2023-06-12 18:24 ` Jerry Snitselaar
2023-06-16 14:31 ` Joerg Roedel [this message]

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