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[142.68.25.194]) by smtp.gmail.com with ESMTPSA id a23-20020a637f17000000b0055b3af821d5sm7758146pgd.25.2023.07.14.10.25.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jul 2023 10:25:52 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.95) (envelope-from ) id 1qKMYB-0018TN-9b; Fri, 14 Jul 2023 14:25:51 -0300 Date: Fri, 14 Jul 2023 14:25:51 -0300 From: Jason Gunthorpe To: Vasant Hegde Cc: iommu@lists.linux.dev, joro@8bytes.org, suravee.suthikulpanit@amd.com Subject: Re: [PATCH 11/21] iommu/amd: Clean up and enhance protection domain flags Message-ID: References: <20230712141516.154144-1-vasant.hegde@amd.com> <20230712141516.154144-12-vasant.hegde@amd.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230712141516.154144-12-vasant.hegde@amd.com> On Wed, Jul 12, 2023 at 02:15:06PM +0000, Vasant Hegde wrote: > From: Suravee Suthikulpanit > > With IOMMU v1 and v2 page tables per domain, and the v2 table can > be used in various modes, keeping track of how a particular domain > is configured becoming cumbersome. > > Enhance protection_domain.flags to keep track of how a domain is > configured. Also Remove unused flags, and rename them accordingly. > > Signed-off-by: Suravee Suthikulpanit > Co-developed-by: Vasant Hegde > Signed-off-by: Vasant Hegde > --- > drivers/iommu/amd/amd_iommu_types.h | 14 +++++--------- > drivers/iommu/amd/io_pgtable_v2.c | 2 +- > drivers/iommu/amd/iommu.c | 21 ++++++++++++--------- > 3 files changed, 18 insertions(+), 19 deletions(-) > > diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h > index 346c32343417..907af6e41ae9 100644 > --- a/drivers/iommu/amd/amd_iommu_types.h > +++ b/drivers/iommu/amd/amd_iommu_types.h > @@ -443,13 +443,11 @@ > #define MAX_DOMAIN_ID 65536 > > /* Protection domain flags */ > -#define PD_DMA_OPS_MASK BIT(0) /* domain used for dma_ops */ > -#define PD_DEFAULT_MASK BIT(1) /* domain is a default dma_ops > - domain for an IOMMU */ > -#define PD_PASSTHROUGH_MASK BIT(2) /* domain has no page > - translation */ > -#define PD_IOMMUV2_MASK BIT(3) /* domain has gcr3 table */ > -#define PD_GIOV_MASK BIT(4) /* domain enable GIOV support */ > +#define PD_FLAG_V1DMA BIT(1) /* DMA-API mode w/ v1 page table */ > +#define PD_FLAG_V2DMA BIT(2) /* DMA-API mode w/ v2 page table */ "DMA-API" should not be part of the driver vocabulary. Does this have anything to do with DMA-API? Only "paging" domains should have IO page tables and an IO page table type. Maybe this is just misnamed? Also, shouldn't it be an enum not flags? > +#define PD_FLAG_PT BIT(0) /* Passthrough mode */ > +#define PD_FLAG_GCR3 BIT(3) /* domain has gcr3 table */ These seem redundant with the domain type? Maybe a few helpers? > +#define PD_FLAG_GIOV BIT(4) /* domain enable GIOV support */ This really shouldn't be a iommu_domain flag, this should be computed based on what domains are attached where Eg this seems like it should be triggered by attaching identity to the RID with PASID enabled or something like that. Why do you need to set it for the legacy GPU path? Jason