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[142.68.25.194]) by smtp.gmail.com with ESMTPSA id x13-20020a0ce24d000000b0063d31b493e1sm647972qvl.99.2023.08.04.06.14.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Aug 2023 06:14:54 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.95) (envelope-from ) id 1qRudp-003icY-IQ; Fri, 04 Aug 2023 10:14:53 -0300 Date: Fri, 4 Aug 2023 10:14:53 -0300 From: Jason Gunthorpe To: Vasant Hegde Cc: iommu@lists.linux.dev, joro@8bytes.org, suravee.suthikulpanit@amd.com, wei.huang2@amd.com, jsnitsel@redhat.com Subject: Re: [PATCH v3 15/16] iommu/amd: Initialize iommu_device->max_pasids Message-ID: References: <20230804064216.835544-1-vasant.hegde@amd.com> <20230804064216.835544-16-vasant.hegde@amd.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230804064216.835544-16-vasant.hegde@amd.com> On Fri, Aug 04, 2023 at 06:42:15AM +0000, Vasant Hegde wrote: > Commit 1adf3cc20d69 ("iommu: Add max_pasids field in struct iommu_device") > introduced a variable struct iommu_device.max_pasids to track max > PASIDS supported by each IOMMU. > > Let us initialize this field for AMD IOMMU. IOMMU core will use this value > to set max PASIDs per device (see __iommu_probe_device()). > > Also remove unused global 'amd_iommu_max_pasid' variable. > > Signed-off-by: Vasant Hegde > --- > drivers/iommu/amd/amd_iommu_types.h | 3 --- > drivers/iommu/amd/init.c | 9 ++------- > 2 files changed, 2 insertions(+), 10 deletions(-) > > diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h > index e114e4af0f05..0d339e022572 100644 > --- a/drivers/iommu/amd/amd_iommu_types.h > +++ b/drivers/iommu/amd/amd_iommu_types.h > @@ -895,9 +895,6 @@ extern unsigned amd_iommu_aperture_order; > /* allocation bitmap for domain ids */ > extern unsigned long *amd_iommu_pd_alloc_bitmap; > > -/* Smallest max PASID supported by any IOMMU in the system */ > -extern u32 amd_iommu_max_pasid; > - > extern bool amd_iommu_force_isolation; > > /* Max levels of glxval supported */ > diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c > index 1f56478ae74e..e0b0e48d3d38 100644 > --- a/drivers/iommu/amd/init.c > +++ b/drivers/iommu/amd/init.c > @@ -185,8 +185,6 @@ static int amd_iommus_present; > bool amd_iommu_np_cache __read_mostly; > bool amd_iommu_iotlb_sup __read_mostly = true; > > -u32 amd_iommu_max_pasid __read_mostly = ~0; > - > static bool amd_iommu_pc_present __read_mostly; > bool amdr_ivrs_remap_support __read_mostly; > > @@ -2086,16 +2084,13 @@ static int __init iommu_init_pci(struct amd_iommu *iommu) > > if (iommu_feature(iommu, FEATURE_GT)) { > int glxval; > - u32 max_pasid; > u64 pasmax; > > pasmax = iommu->features & FEATURE_PASID_MASK; > pasmax >>= FEATURE_PASID_SHIFT; > - max_pasid = (1 << (pasmax + 1)) - 1; > - > - amd_iommu_max_pasid = min(amd_iommu_max_pasid, max_pasid); > + iommu->iommu.max_pasids = (1 << (pasmax + 1)) - 1; > > - BUG_ON(amd_iommu_max_pasid & ~PASID_MASK); > + BUG_ON(iommu->iommu.max_pasids & ~PASID_MASK); You said you'd fix this to remove the BUG_ON. Jason