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[142.68.25.194]) by smtp.gmail.com with ESMTPSA id a24-20020a637058000000b0056c2843d80dsm5816935pgn.10.2023.08.23.08.36.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Aug 2023 08:36:03 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.95) (envelope-from ) id 1qYptq-00HTpm-2k; Wed, 23 Aug 2023 12:36:02 -0300 Date: Wed, 23 Aug 2023 12:36:02 -0300 From: Jason Gunthorpe To: Vasant Hegde Cc: iommu@lists.linux.dev, joro@8bytes.org, suravee.suthikulpanit@amd.com, wei.huang2@amd.com, jsnitsel@redhat.com Subject: Re: [PATCH RESEND 10/10] iommu/amd: Introduce logic to enable/disable IOPF Message-ID: References: <20230823140415.729050-1-vasant.hegde@amd.com> <20230823140415.729050-11-vasant.hegde@amd.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230823140415.729050-11-vasant.hegde@amd.com> On Wed, Aug 23, 2023 at 02:04:15PM +0000, Vasant Hegde wrote: > diff --git a/drivers/iommu/amd/ppr.c b/drivers/iommu/amd/ppr.c > index db4fa4534cd6..8c197b768b4a 100644 > --- a/drivers/iommu/amd/ppr.c > +++ b/drivers/iommu/amd/ppr.c > @@ -9,6 +9,7 @@ > #include > #include > #include > +#include > > #include "amd_iommu.h" > #include "amd_iommu_types.h" > @@ -319,3 +320,58 @@ int amd_iommu_iopf_remove_device(struct amd_iommu *iommu, struct device *dev) > raw_spin_unlock_irqrestore(&iommu->lock, flags); > return ret; > } > + > +static int amd_iommu_iopf_update(struct device *dev, bool enable) > +{ > + unsigned long flags; > + int ret; > + struct pci_dev *pdev = dev_is_pci(dev) ? to_pci_dev(dev) : NULL; > + struct amd_iommu *iommu = get_amd_iommu_from_dev(dev); > + struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev); > + struct protection_domain *pdom = amd_iommu_get_pdomain(dev); > + > + if (!pdev || !iommu || !dev_data) > + return -EINVAL; > + > + spin_lock_irqsave(&pdom->lock, flags); > + > + if (enable) { > + ret = amd_iommu_iopf_add_device(iommu, dev); > + if (ret) > + goto out; > + > + dev_data->ppr = true; > + } else { > + ret = amd_iommu_iopf_remove_device(iommu, dev); > + dev_data->ppr = false; > + } > + > + amd_iommu_domain_update(pdom); > + > +out: > + spin_unlock_irqrestore(&pdom->lock, flags); > + return ret; > +} > + > +int amd_iommu_iopf_enable(struct device *dev) > +{ > + struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev); > + > + if (!(dev_data->flags & AMD_IOMMU_DEVICE_FLAG_PRI_SUP)) > + return -ENODEV; > + > + if (!dev_data->ats_enabled || !dev_data->pri_enabled) > + return -EINVAL; > + > + return amd_iommu_iopf_update(dev, true); > +} > + > +int amd_iommu_iopf_disable(struct device *dev) > +{ > + struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev); > + > + if (!dev_data->pri_enabled) > + return -EINVAL; > + > + return amd_iommu_iopf_update(dev, false); > +} These features also look like a mistake.. PRI is enabled if the domain has an iopf handler, when that domain is attached to the RID/PASID. It remains enabled so long as any IOPF enabled domain is present on the device. So again, these should be checks but otherwise NOPs and any actual working has to be pushed into the domain attach code. Jason