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Tue, 4 Jun 2024 11:28:07 -0700 Date: Tue, 4 Jun 2024 11:28:05 -0700 From: Nicolin Chen To: Jason Gunthorpe CC: , Joerg Roedel , , Robin Murphy , Will Deacon , Michael Shavit , , Ryan Roberts , Mostafa Saleh Subject: Re: [PATCH 1/7] iommu/arm-smmu-v3: Split struct arm_smmu_strtab_cfg.strtab Message-ID: References: <0-v1-1b720dce51d1+4f44-smmuv3_tidy_jgg@nvidia.com> <1-v1-1b720dce51d1+4f44-smmuv3_tidy_jgg@nvidia.com> <20240604125955.GH19897@nvidia.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20240604125955.GH19897@nvidia.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B069:EE_|PH7PR12MB5654:EE_ X-MS-Office365-Filtering-Correlation-Id: 3835a1bf-d283-4a2b-ffae-08dc84c42485 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|82310400017|36860700004|376005|1800799015; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jun 2024 18:28:33.8954 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3835a1bf-d283-4a2b-ffae-08dc84c42485 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B069.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5654 On Tue, Jun 04, 2024 at 09:59:55AM -0300, Jason Gunthorpe wrote: > On Tue, Jun 04, 2024 at 01:32:20AM -0700, Nicolin Chen wrote: > > On Mon, Jun 03, 2024 at 07:31:27PM -0300, Jason Gunthorpe wrote: > > > > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > > > index 1242a086c9f948..4769780259affc 100644 > > > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > > > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > > > @@ -612,7 +610,10 @@ struct arm_smmu_s2_cfg { > > > }; > > > > > > struct arm_smmu_strtab_cfg { > > > - __le64 *strtab; > > > + union { > > > + struct arm_smmu_ste *linear; > > > + __le64 *l1_desc; > > > + } strtab; > > > dma_addr_t strtab_dma; > > > struct arm_smmu_strtab_l1_desc *l1_desc; > > > unsigned int num_l1_ents; > > > > It looks like we have two "l1_desc" ptrs now in the same struct: > > strtab.l1_desc // raw level-1 descriptor memory > > l1_desc // SW array to store level-2 descriptor memory > > > > And it gets a bit more confusing that they even use the same error > > prints in arm_smmu_init_strtab_2lvl()... > > Yeah, I noticed that too, but failed to come with better names.. The > CD has the same issue > > strtab.l1_desc is a pointer to the data structure that the HW fetches > that is the first level of a 2 level strtab, it stores an encoded > dma_addr_t. > > cfg.l1_desc is an array of CPU information for each HW L1 entry, > eventually just being the CPU pointer to the L2 STE table. > > So they are both the l1 array, just one is a CPU pointer and one is a > HW/DMA pointer. > > Let's call strtab.l1_desc --> strtab.l1_table ? Yea. This seems to be good. > > The "struct arm_smmu_strtab_l1_desc" seems to be only used at one > > place in arm_smmu_init_l2_strtab(). So, how about: > > I didn't do it but, it would make some of the maths more obvious > if we encoded the table structure in the types: > > struct arm_smmu_strtab_l2_stes { > struct arm_smmu_ste l2[256]; > }; I personally prefer this one, though why 256? I was also thinking of an alternative by separating linear/2lvl: struct arm_smmu_ste { __le64 data[8]; }; struct arm_smmu_strtab_linear { struct arm_smmu_ste *ste; dma_addr_t ste_dma; }; struct arm_smmu_strtab_l1_desc { // so as to drop TRTAB_L1_DESC_DWORDS __le64 data; }; struct arm_smmu_strtab_l2_stes { struct arm_smmu_ste *ste; }; struct arm_smmu_strtab_l1 { struct arm_smmu_strtab_l1_desc *l1; dma_addr_t l1_dma; struct arm_smmu_strtab_l2_stes *l2; }; struct arm_smmu_device { ... union { struct arm_smmu_strtab_linear linear; struct arm_smmu_strtab_l1 l1; } strtab; ... }; Only arm_smmu_device_reset() really needs strtab_base/_cfg values that we could compute them over there, given that there are quite amount of smmu->features checking already? Thanks Nicolin