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Thu, 6 Jun 2024 16:47:58 -0700 Date: Thu, 6 Jun 2024 16:47:57 -0700 From: Nicolin Chen To: Shameer Kolothum CC: , , , , , , , , , , , , , Subject: Re: [PATCH v5 6/6] iommu/arm-smmu-v3: Enable HTTU for stage1 with io-pgtable mapping Message-ID: References: <20240606133302.17540-1-shameerali.kolothum.thodi@huawei.com> <20240606133302.17540-7-shameerali.kolothum.thodi@huawei.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20240606133302.17540-7-shameerali.kolothum.thodi@huawei.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9DB:EE_|SJ1PR12MB6097:EE_ X-MS-Office365-Filtering-Correlation-Id: be924fb1-7326-4cc2-1cc6-08dc86832039 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|376005|36860700004|1800799015|7416005|82310400017; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2024 23:48:11.8281 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: be924fb1-7326-4cc2-1cc6-08dc86832039 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9DB.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6097 On Thu, Jun 06, 2024 at 02:33:02PM +0100, Shameer Kolothum wrote: > From: Kunkun Jiang > > If io-pgtable quirk flag indicates support for hardware update of > dirty state, enable HA/HD bits in the SMMU CD and also set the DBM > bit in the page descriptor. > > Now report the dirty page tracking capability of SMMUv3 and > select IOMMUFD_DRIVER for ARM_SMMU_V3 if IOMMUFD is enabled. > > Co-developed-by: Keqian Zhu > Signed-off-by: Keqian Zhu > Signed-off-by: Kunkun Jiang > Signed-off-by: Joao Martins > Reviewed-by: Ryan Roberts > Reviewed-by: Jason Gunthorpe > Signed-off-by: Shameer Kolothum Reviewed-by: Nicolin Chen With a nit: > +static bool arm_smmu_dbm_capable(struct arm_smmu_device *smmu) > +{ > + u32 features = (ARM_SMMU_FEAT_HD | ARM_SMMU_FEAT_COHERENCY); > + > + return (smmu->features & features) == features; Following the existing coding style in the driver: return (smmu->features & ARM_SMMU_FEAT_HD) && (smmu->features & ARM_SMMU_FEAT_COHERENCY); And inline? Thanks Nicolin