From: Baolu Lu <baolu.lu@linux.intel.com>
To: Tina Zhang <tina.zhang@intel.com>, iommu@lists.linux.dev
Cc: baolu.lu@linux.intel.com
Subject: Re: [PATCH v2] iommu/vt-d: Set SRE bit when hardware has SRS cap
Date: Wed, 16 Nov 2022 13:19:39 +0800 [thread overview]
Message-ID: <a1e899b2-4e96-1b3c-27b1-cc29d629e3ea@linux.intel.com> (raw)
In-Reply-To: <20221115070346.1112273-1-tina.zhang@intel.com>
On 11/15/22 3:03 PM, Tina Zhang wrote:
> SRS cap is the hardware cap telling if the hardware IOMMU can support
> requests seeking supervisor privilege or not. SRE bit in scalable-mode
> PASID table entry is treated as Reserved(0) for implementation not
> supporting SRS cap.
>
> Checking SRS cap before setting SRE bit can avoid the non-recoverable
> fault of "Non-zero reserved field set in PASID Table Entry" caused by
> setting SRE bit while there is no SRS cap support.
>
> V2: Add SRS cap checking in intel_pasid_setup_second_level()
>
> Fixes: 6f7db75e1c46 ("iommu/vt-d: Add second level page table interface")
> Signed-off-by: Tina Zhang<tina.zhang@intel.com>
Patch queued for v6.1. Thank you!
https://lore.kernel.org/linux-iommu/20221116051544.26540-1-baolu.lu@linux.intel.com/
Best regards,
baolu
prev parent reply other threads:[~2022-11-16 5:26 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-15 7:03 [PATCH v2] iommu/vt-d: Set SRE bit when hardware has SRS cap Tina Zhang
2022-11-16 5:19 ` Baolu Lu [this message]
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