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[146.148.24.157]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45e41b6dbdbsm211187025e9.22.2025.09.16.08.19.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 08:19:06 -0700 (PDT) Date: Tue, 16 Sep 2025 15:19:02 +0000 From: Mostafa Saleh To: Jason Gunthorpe Cc: Will Deacon , linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, maz@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, robin.murphy@arm.com, jean-philippe@linaro.org, qperret@google.com, tabba@google.com, mark.rutland@arm.com, praan@google.com Subject: Re: [PATCH v4 22/28] iommu/arm-smmu-v3-kvm: Emulate CMDQ for host Message-ID: References: <20250819215156.2494305-1-smostafa@google.com> <20250819215156.2494305-23-smostafa@google.com> <20250915163858.GK882933@ziepe.ca> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250915163858.GK882933@ziepe.ca> On Mon, Sep 15, 2025 at 01:38:58PM -0300, Jason Gunthorpe wrote: > On Fri, Sep 12, 2025 at 03:18:08PM +0100, Will Deacon wrote: > > Ideally, the data structures that are shadowed by the hypervisor would > > be mapped as normal-WB cacheable in both the host and the hypervisor so > > we don't have to worry about coherency and we get the performance > > benefits from the caches. Indeed, I think that's how you've mapped > > 'host_cmdq' above _however_ I sadly don't think we can do that if the > > actual SMMU hardware isn't coherent. > > That seems like the right conclusion to me, pkvm should not be mapping > as cachable unless it knows the IORT/IDR is marked as coherent. > > This is actually something I want to fix in the SMMU driver, it should > always be allocating cachable memory and using > dma_sync_single_for_device() instead of non-cachable DMA coherent > allocations. (Or perhaps better is to use > iommu_pages_flush_incoherent()) > > I'm hearing about an interesting use case where we'd want to tell the > SMMU to walk STEs non-cachable even if the HW is capable to do > cachable. Apparently in some SOCs it gives better isochronous > properties for realtime DMA. Interesting, I guess that would be more noticable for the page table walks rather than the STE, as Linux doesn't invalidate STEs that much. > > > IMHO for this series at this point pkvm should just require a coherent > SMMU until the above revisions happen. I think the fix for the problem Will mentioned is to just use CMOs before accessing the host structures, so that should be simple. If it turns to be more complicated, I am happy to drop the support for non-coherent devices from this series and we can add it later. Thanks, Mostafa > > Jason