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Sat, 6 Dec 2025 11:45:41 -0800 Date: Sat, 6 Dec 2025 11:45:40 -0800 From: Nicolin Chen To: Jason Gunthorpe CC: , , , , , , , Subject: Re: [PATCH rc v1 1/4] iommu/arm-smmu-v3: Add ignored bits to fix STE update sequence Message-ID: References: <6ec73bb7cd03d90a0764f12c4b14071158163818.1764982046.git.nicolinc@nvidia.com> <20251206193408.GD1219718@nvidia.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20251206193408.GD1219718@nvidia.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A0FC:EE_|LV8PR12MB9405:EE_ X-MS-Office365-Filtering-Correlation-Id: 03bd2628-0a92-4c9c-4e96-08de35000c0f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?qCGAB40/TQKyAUhPGIdsXreWZrVYRZCnlVSneYtoqCUD4leoSmZrC5nrEDDu?= =?us-ascii?Q?qCri9e2V7yOdR2PzEXqvCqYAqVTq2VhyT+wzTqJ6ccmW2VrQkwblfFOOMda8?= =?us-ascii?Q?iETkw5IK7Y27Dc3OFPP+2GbP3u47NOOlWYznOfD5/0uE87Pm2wgPpOTwyG7Y?= =?us-ascii?Q?G6w8KxIUYKoaJ9YpOsq91w+aG37c4T/bk9aHYgOy87JrCYj+4E2Bpg9wzRdZ?= =?us-ascii?Q?Ffil2UNwcEkpDLIxzFEG84dZQPrg2oW18hBVc/M97M6giQdxDlqSw4au4atk?= =?us-ascii?Q?Ug5Ka/ZF5muNL11XnSCRfMedY/gqSCEWcyS1yZXc8G7P1OGZXkN7i4u0z/vj?= =?us-ascii?Q?dvcG+N1YnqYrChAoigKy/Li1yyaZgof+iuO43utIfv0IJn0NQXCM5N++OO+q?= =?us-ascii?Q?D46PixihPAZm5cqdLPxxrqhzzO8uHFKDhUmCH0F2Mh4gkT6A2aWouN6uPwQF?= =?us-ascii?Q?r8yPsStmY0Xbe/Q7qR2zMLTcknot+X3+dPX78RW0G8FP7O7g2KzzrMwpg7VH?= =?us-ascii?Q?+DiksjdxGv+Ldag0ejmwRHtLTFsYUelEoYSbLVvS/nG8xgck2encHEFkt6l+?= =?us-ascii?Q?i2ZgdsRv8XlnpM0BN8IiXYcB/oKihVQpUNG7tLtQP8V2WWMJCeQv2QGXDBoc?= =?us-ascii?Q?P6+MiRR+Zp+F8YbyIjT3ZuSko18oDt7N8ipCdWxdrmmOmv9JbevoBj2IO5nx?= =?us-ascii?Q?JNm/J7OVGyTD8UHAh6tWDM7qcFPrMBSwQLgZ0BwBXf48c+2eLKNz7cqzcxDK?= =?us-ascii?Q?PZNOiVioaUokpgQf7/O2a1xSyi1U8Hl56nUeX0sgmDjOjGljG4iH9OAuQIbI?= =?us-ascii?Q?RmZoKGTkAesWNVOF9SDPWOu44ALdt8enGHvgnSPfECxGeaRJO0DXDrFSSI4W?= =?us-ascii?Q?lPOFS/ebwsC4KdUVPedgh+4o95IvCMMG1Vm2LUp+VbZKlbTWJkCrtSEq9z4G?= =?us-ascii?Q?k6pzsCXcf2o8nQUlpGPDSwvhnYqk20hrON3nCjgliuvHh0KPtfGaeU6o3PB/?= =?us-ascii?Q?fG0bDAjNZigu0MUwJ1dxH4njz+Ac0ZD3mpzU2RSvuWhNEciPzsa4ROscEUIL?= =?us-ascii?Q?xcq/XrJ9gU31QdScbWubR6WmcM10fkIRbwU35m8YA1wxhHbeVpe4OXosgiY2?= =?us-ascii?Q?SRkY522DrtGw3fwBC10le6yDvDfdAD2mgl9iEM1Qmz2ViYgvoynsY/JYJW7t?= =?us-ascii?Q?h37rujZsSE8WFT9If72fVEYs8+Tcqis+GDViUPod8JlH8D56rI5amFU00N4+?= =?us-ascii?Q?BfAdh5zx09phS8MgdRgxHR58TdQE4CuO0PlbfZbc0wyapCNrmV7ZLn/Ng6m/?= =?us-ascii?Q?by+2zlJr287QmhGz2ofQDwk3oKTiUQJVec+UtkzObdA8sZ04U+HooKEYrjGk?= =?us-ascii?Q?oR1AwVPJqbJ5sXSYqZZjpi90BX33X5X2xQudWZcoJGEZhGu7mhaxPtcBTVHi?= =?us-ascii?Q?PkzKHOrp45PaHQZqzHJsBfPmO42/xM2d0Cx4LWy/LCVuEy3c2OUfYcenZ7gw?= =?us-ascii?Q?rn91PizTXqalsxa2A/dZYYQNppK6kL9rNgLiqoigtOI0rzTjY4C45wgw8w?= =?us-ascii?Q?=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Dec 2025 19:45:44.9801 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 03bd2628-0a92-4c9c-4e96-08de35000c0f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0FC.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9405 On Sat, Dec 06, 2025 at 03:34:08PM -0400, Jason Gunthorpe wrote: > On Fri, Dec 05, 2025 at 04:52:00PM -0800, Nicolin Chen wrote: > > @@ -1106,16 +1115,17 @@ static u8 arm_smmu_entry_qword_diff(struct arm_smmu_entry_writer *writer, > > * allowed to set a bit to 1 if the used function doesn't say it > > * is used. > > */ > > - WARN_ON_ONCE(target[i] & ~target_used[i]); > > + WARN_ON_ONCE(target[i] & ~target_used[i] & ~ignored[i]); > > > > /* Bits can change because they are not currently being used */ > > - unused_update[i] = (entry[i] & cur_used[i]) | > > + unused_update[i] = (entry[i] & (cur_used[i] | ignored[i])) | > > (target[i] & ~cur_used[i]); > > This can't be right? We don't want to ever copy an ignored bit from > entry, the ignored bits should always come from target. The line > should be left alone. Hmm, without this change, the following coverages will be broken: arm_smmu_v3_write_ste_test_s1dssbypass_to_stebypass arm_smmu_v3_write_ste_test_stebypass_to_s1dssbypass Both were expect num_syncs=2, but it would be 3 if we don't include the ignored bits to unused_update. Or should we update the num_syncs instead? Nicolin