Re: [PATCH v9 0/7] iommu/arm-smmu-v3: Introduce an RCU-protected invalidation array

Nicolin Chen
2026-01-19T17:10:21Z

Hi Will,

On Fri, Dec 19, 2025 at 12:11:22PM -0800, Nicolin Chen wrote:
> * NVIDIA is building systems with > 10 SMMU instances where > 8 are being
> used concurrently in a single VM. So having 8 copies of an identical S2
> page table is not efficient. Instead, all vSMMU instances should check
> compatibility on a shared S2 iopt, to eliminate 7 copies.
>
> Previous attempt based on the list/spinlock design:
> iommu/arm-smmu-v3: Allocate vmid per vsmmu instead of s2_parent
> https://lore.kernel.org/all/cover.1744692494.git.nicolinc@nvidia.com/
> now can adopt this invs array, avoiding adding complex lists/locks.
>
> * The guest support for BTM requires temporarily invalidating two ASIDs
> for a single instance. When it renumbers ASIDs this can now be done via
> the invs array.
>
> * SVA with multiple devices being used by a single process (NVIDIA today
> has 4-8) sequentially iterates the invalidations through all instances.
> This ignores the HW concurrency available in each instance. It would be
> nice to not spin on each sync but go forward and issue batches to other
> instances also. Reducing to a single SVA domain shared across instances
> is required to look at this.
>
> This is on Github:
> https://github.com/nicolinc/iommufd/commits/arm_smmu_invs-v9
>
> Changelog
> v9:
> * Set cur->ssid correctly in arm_smmu_master_build_inv()
> * Add comments for INV_TYPE_S1_ASID in arm_smmu_master_build_inv()

Sorry for a gentle push. This has been sitting here for a while.
And we are at rc6. Any chance that it can make it to this cycle?

We have a dependent series that I am about to send v2:
https://lore.kernel.org/linux-iommu/cover.1766088962.git.nicolinc@nvidia.com/

Anything that you think I should improve, please let me know.

Thanks!
Nicolin