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Wed, 14 Jan 2026 02:55:40 -0800 (PST) Received: from mitya-t14-2025 ([2a02:a31b:20c3:6680:8f9d:1786:e151:a9f5]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b86ebfd007fsm1281735566b.31.2026.01.14.02.55.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jan 2026 02:55:39 -0800 (PST) Date: Wed, 14 Jan 2026 11:55:36 +0100 From: Dmytro Maluka To: Baolu Lu Cc: Joerg Roedel , Will Deacon , Robin Murphy , Kevin Tian , Jason Gunthorpe , Samiullah Khawaja , iommu@lists.linux.dev, linux-kernel@vger.kernel.org, "Vineeth Pillai (Google)" , Aashish Sharma Subject: Re: [PATCH 1/3] iommu/vt-d: Use 128-bit atomic updates for context entries Message-ID: References: <20260113030052.977366-1-baolu.lu@linux.intel.com> <20260113030052.977366-2-baolu.lu@linux.intel.com> <1e967054-d2bd-4c3d-99eb-315a40bac9de@linux.intel.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1e967054-d2bd-4c3d-99eb-315a40bac9de@linux.intel.com> On Wed, Jan 14, 2026 at 01:14:36PM +0800, Baolu Lu wrote: > On 1/14/26 03:27, Dmytro Maluka wrote: > > On Tue, Jan 13, 2026 at 11:00:46AM +0800, Lu Baolu wrote: > > > +static __always_inline void intel_iommu_atomic128_set(u128 *ptr, u128 val) > > > +{ > > > + /* > > > + * Use the cmpxchg16b instruction for 128-bit atomicity. As updates > > > + * are serialized by a spinlock, we use the local (unlocked) variant > > > + * to avoid unnecessary bus locking overhead. > > > + */ > > > + arch_cmpxchg128_local(ptr, *ptr, val); > > Any reason why not cmpxchg128_local()? (except following the AMD driver) > > Yes. This follows the AMD IOMMU driver. Both drivers use spin lock to > synchronize the update of table entries. They only need the atomicity of > the 128-bit instruction itself. So arch_cmpxchg128_local() works. Yeah, but my question was merely: why use the raw arch_*() version, not cmpxchg128_local() which is the same but also includes optional kasan/kcsan instrumentation: #define cmpxchg128_local(ptr, ...) \ ({ \ typeof(ptr) __ai_ptr = (ptr); \ instrument_atomic_read_write(__ai_ptr, sizeof(*__ai_ptr)); \ raw_cmpxchg128_local(__ai_ptr, __VA_ARGS__); \ }) IOW, why bypass this instrumentation?