[PATCH 5/8] iommu/vt-d: Use intel_pasid_write() for first-stage setup

Lu Baolu
2026-03-09T06:09:55Z

Refactor intel_pasid_setup_first_level() to utilize the intel_pasid_write()
helper. By moving to the entry_sync library, the driver now constructs the
target entry in a local buffer and hands it off to intel_pasid_write().

This refactoring removes the need for __domain_setup_first_level(),
simplifies locking by using the group mutex, and ensures a consistent
update path for all first-stage setups.

Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
---
drivers/iommu/intel/iommu.h | 5 -----
drivers/iommu/intel/iommu.c | 16 +++-------------
drivers/iommu/intel/pasid.c | 36 +++++++++---------------------------
drivers/iommu/intel/svm.c | 5 ++---
4 files changed, 14 insertions(+), 48 deletions(-)

diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h
index 54b58d01d0cb..fd6ca3b7f594 100644
--- a/drivers/iommu/intel/iommu.h
+++ b/drivers/iommu/intel/iommu.h
@@ -1202,11 +1202,6 @@ domain_add_dev_pasid(struct iommu_domain *domain,
struct device *dev, ioasid_t pasid);
void domain_remove_dev_pasid(struct iommu_domain *domain,
struct device *dev, ioasid_t pasid);
-
-int __domain_setup_first_level(struct intel_iommu *iommu, struct device *dev,
- ioasid_t pasid, u16 did, phys_addr_t fsptptr,
- int flags, struct iommu_domain *old);
-
int dmar_ir_support(void);

void iommu_flush_write_buffer(struct intel_iommu *iommu);
diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index 5369526e89d0..db5e8dad50dc 100644
--- a/drivers/iommu/intel/iommu.c
+++ b/drivers/iommu/intel/iommu.c
@@ -1248,16 +1248,6 @@ static void domain_context_clear_one(struct device_domain_info *info, u8 bus, u8
__iommu_flush_cache(iommu, context, sizeof(*context));
}

-int __domain_setup_first_level(struct intel_iommu *iommu, struct device *dev,
- ioasid_t pasid, u16 did, phys_addr_t fsptptr,
- int flags, struct iommu_domain *old)
-{
- if (old)
- intel_pasid_tear_down_entry(iommu, dev, pasid, false);
-
- return intel_pasid_setup_first_level(iommu, dev, fsptptr, pasid, did, flags);
-}
-
static int domain_setup_second_level(struct intel_iommu *iommu,
struct dmar_domain *domain,
struct device *dev, ioasid_t pasid,
@@ -1301,9 +1291,9 @@ static int domain_setup_first_level(struct intel_iommu *iommu,
BIT(PT_FEAT_DMA_INCOHERENT)))
flags |= PASID_FLAG_PWSNP;

- return __domain_setup_first_level(iommu, dev, pasid,
- domain_id_iommu(domain, iommu),
- pt_info.gcr3_pt, flags, old);
+ return intel_pasid_setup_first_level(iommu, dev, pt_info.gcr3_pt, pasid,
+ domain_id_iommu(domain, iommu),
+ flags);
}

static int dmar_domain_attach_device(struct dmar_domain *domain,
diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c
index b7c8888afaef..8ea1ac8cbf5e 100644
--- a/drivers/iommu/intel/pasid.c
+++ b/drivers/iommu/intel/pasid.c
@@ -172,9 +172,8 @@ static const struct entry_sync_writer_ops128 writer_ops128 = {

#define INTEL_PASID_SYNC_MEM_COUNT 12

-static int __maybe_unused intel_pasid_write(struct intel_iommu *iommu,
- struct device *dev, u32 pasid,
- u128 *target)
+static int intel_pasid_write(struct intel_iommu *iommu, struct device *dev,
+ u32 pasid, u128 *target)
{
struct pasid_entry *pte = intel_pasid_get_entry(dev, pasid);
struct intel_pasid_writer p_writer = {
@@ -531,17 +530,14 @@ static void intel_pasid_flush_present(struct intel_iommu *iommu,

/*
* Set up the scalable mode pasid table entry for first only
- * translation type.
+ * translation type. Caller should zero out the entry before
+ * calling.
*/
static void pasid_pte_config_first_level(struct intel_iommu *iommu,
struct pasid_entry *pte,
phys_addr_t fsptptr, u16 did,
int flags)
{
- lockdep_assert_held(&iommu->lock);
-
- pasid_clear_entry(pte);
-
/* Setup the first level page table pointer: */
pasid_set_flptr(pte, fsptptr);

@@ -564,7 +560,9 @@ int intel_pasid_setup_first_level(struct intel_iommu *iommu, struct device *dev,
phys_addr_t fsptptr, u32 pasid, u16 did,
int flags)
{
- struct pasid_entry *pte;
+ struct pasid_entry new_pte = {0};
+
+ iommu_group_mutex_assert(dev);

if (!ecap_flts(iommu->ecap)) {
pr_err("No first level translation support on %s\n",
@@ -578,25 +576,9 @@ int intel_pasid_setup_first_level(struct intel_iommu *iommu, struct device *dev,
return -EINVAL;
}

- spin_lock(&iommu->lock);
- pte = intel_pasid_get_entry(dev, pasid);
- if (!pte) {
- spin_unlock(&iommu->lock);
- return -ENODEV;
- }
+ pasid_pte_config_first_level(iommu, &new_pte, fsptptr, did, flags);

- if (pasid_pte_is_present(pte)) {
- spin_unlock(&iommu->lock);
- return -EBUSY;
- }
-
- pasid_pte_config_first_level(iommu, pte, fsptptr, did, flags);
-
- spin_unlock(&iommu->lock);
-
- pasid_flush_caches(iommu, pte, pasid, did);
-
- return 0;
+ return intel_pasid_write(iommu, dev, pasid, (u128 *)&new_pte);
}

/*
diff --git a/drivers/iommu/intel/svm.c b/drivers/iommu/intel/svm.c
index fea10acd4f02..978d63073e3b 100644
--- a/drivers/iommu/intel/svm.c
+++ b/drivers/iommu/intel/svm.c
@@ -171,9 +171,8 @@ static int intel_svm_set_dev_pasid(struct iommu_domain *domain,
/* Setup the pasid table: */
sflags = cpu_feature_enabled(X86_FEATURE_LA57) ? PASID_FLAG_FL5LP : 0;
sflags |= PASID_FLAG_PWSNP;
- ret = __domain_setup_first_level(iommu, dev, pasid,
- FLPT_DEFAULT_DID, __pa(mm->pgd),
- sflags, old);
+ ret = intel_pasid_setup_first_level(iommu, dev, __pa(mm->pgd),
+ pasid, FLPT_DEFAULT_DID, sflags);
if (ret)
goto out_unwind_iopf;

--
2.43.0