[PATCH 19/22] iommu/amd: Add support for vIOMMU HW queues initialization

Suravee Suthikulpanit
2026-03-30T08:44:26Z

AMD HW vIOMMU supports virtualizing Command buffer, Event log, and PPR log.
Each can be initialized using the struct iommufd_viommu_ops.hw_queue_init
to communicate base address (GPA) and length of each queue to the AMD IOMMU
driver in order to programe the corresponded VF control MMIO registers.

Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
---
drivers/iommu/amd/amd_iommu_types.h | 4 ++
drivers/iommu/amd/iommufd.c | 68 +++++++++++++++++++++++++++++
include/uapi/linux/iommufd.h | 3 ++
3 files changed, 75 insertions(+)

diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
index 2c4844b44caf..1cd50a4008fb 100644
--- a/drivers/iommu/amd/amd_iommu_types.h
+++ b/drivers/iommu/amd/amd_iommu_types.h
@@ -1127,6 +1127,10 @@ struct amd_iommu_vdevice {
struct iommufd_vdevice core;
};

+struct amd_iommu_hw_queue {
+ struct iommufd_hw_queue core;
+};
+
#ifdef CONFIG_IRQ_REMAP
extern struct amd_irte_ops irte_32_ops;
extern struct amd_irte_ops irte_128_ops;
diff --git a/drivers/iommu/amd/iommufd.c b/drivers/iommu/amd/iommufd.c
index f83d69716eaa..6f766254a390 100644
--- a/drivers/iommu/amd/iommufd.c
+++ b/drivers/iommu/amd/iommufd.c
@@ -165,6 +165,72 @@ static int _amd_viommu_vdevice_init(struct iommufd_vdevice *vdev)
return 0;
}

+static size_t _amd_viommu_get_hw_queue_size(struct iommufd_viommu *viommu,
+ enum iommu_hw_queue_type queue_type)
+{
+ /* Currently do not support Eventlog B and PPRlog B */
+ if ((queue_type != IOMMU_HW_QUEUE_TYPE_AMD_CMD) &&
+ (queue_type != IOMMU_HW_QUEUE_TYPE_AMD_EVT) &&
+ (queue_type != IOMMU_HW_QUEUE_TYPE_AMD_PPR))
+ return 0;
+
+ return HW_QUEUE_STRUCT_SIZE(struct amd_iommu_hw_queue, core);
+}
+
+static int _amd_viommu_hw_queue_init(struct iommufd_hw_queue *hw_queue, u32 index)
+{
+ int ret = 0;
+ u64 val, tmp;
+ u8 __iomem *vfctrl, *vf;
+ struct iommufd_viommu *viommu = hw_queue->viommu;
+ struct amd_iommu_viommu *aviommu = container_of(viommu, struct amd_iommu_viommu, core);
+ struct amd_iommu *iommu = container_of(viommu->iommu_dev, struct amd_iommu, iommu);
+ int gid = aviommu->gid;
+
+ vf = VIOMMU_VF_MMIO_BASE(iommu, gid);
+ vfctrl = VIOMMU_VFCTRL_MMIO_BASE(iommu, gid);
+
+ switch (hw_queue->type) {
+ case IOMMU_HW_QUEUE_TYPE_AMD_CMD:
+ {
+ val = readq(vfctrl + 0x20);
+ val &= ~(0xFFFFFFFFFF00FULL);
+ tmp = (hw_queue->length & 0xFULL);
+ val = tmp | (hw_queue->base_addr & 0xFFFFFFFFFF000ULL);
+
+ writeq(val, vfctrl + 0x20);
+ break;
+ }
+ case IOMMU_HW_QUEUE_TYPE_AMD_EVT:
+ {
+ val = readq(vfctrl + 0x28);
+ val &= ~(0xFFFFFFFFFF00FULL);
+ tmp = (hw_queue->length & 0xFULL);
+ val = tmp | (hw_queue->base_addr & 0xFFFFFFFFFF000ULL);
+ writeq(val, vfctrl + 0x28);
+ break;
+ }
+ case IOMMU_HW_QUEUE_TYPE_AMD_PPR:
+ {
+ val = readq(vfctrl + 0x30);
+ val &= ~(0xFFFFFFFFFF00FULL);
+ tmp = (hw_queue->length & 0xFULL);
+ val = tmp | ((hw_queue->base_addr & 0xFFFFFFFFFF000ULL) << 4);
+ writeq(val, vfctrl + 0x30);
+ break;
+ }
+ default:
+ pr_err("%s: Invalid type (%#x)\n", __func__, hw_queue->type);
+ return -EINVAL;
+ }
+
+ pr_debug("%s: iommu_devid=%#x, gid=%#x, type=%#x, addr=%#llx, len=%#lx, val=%#llx\n",
+ __func__, iommu->devid, gid, hw_queue->type,
+ hw_queue->base_addr, hw_queue->length, val);
+
+ return ret;
+}
+
/*
* See include/linux/iommufd.h
* struct iommufd_viommu_ops - vIOMMU specific operations
@@ -174,4 +240,6 @@ static const struct iommufd_viommu_ops amd_viommu_ops = {
.destroy = amd_iommufd_viommu_destroy,
.vdevice_size = VDEVICE_STRUCT_SIZE(struct amd_iommu_vdevice, core),
.vdevice_init = _amd_viommu_vdevice_init,
+ .get_hw_queue_size = _amd_viommu_get_hw_queue_size,
+ .hw_queue_init = _amd_viommu_hw_queue_init,
};
diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h
index d9e5c5f0d997..f71a4b979d52 100644
--- a/include/uapi/linux/iommufd.h
+++ b/include/uapi/linux/iommufd.h
@@ -1317,6 +1317,9 @@ enum iommu_hw_queue_type {
* emulated vSMMU's IDR1.CMDQS to log2(huge page size / 16 bytes)
*/
IOMMU_HW_QUEUE_TYPE_TEGRA241_CMDQV = 1,
+ IOMMU_HW_QUEUE_TYPE_AMD_CMD,
+ IOMMU_HW_QUEUE_TYPE_AMD_EVT,
+ IOMMU_HW_QUEUE_TYPE_AMD_PPR,
};

/**
--
2.34.1