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([2404:f801:9000:1a:efea::50b]) by smtp.gmail.com with ESMTPSA id h13sm6970553pgh.93.2021.08.27.10.46.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 27 Aug 2021 10:47:00 -0700 (PDT) Subject: Re: [PATCH V4 05/13] hyperv: Add Write/Read MSR registers via ghcb page To: Greg KH References: <20210827172114.414281-1-ltykernel@gmail.com> <20210827172114.414281-6-ltykernel@gmail.com> From: Tianyu Lan Message-ID: Date: Sat, 28 Aug 2021 01:46:44 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US Cc: parri.andrea@gmail.com, linux-hyperv@vger.kernel.org, brijesh.singh@amd.com, peterz@infradead.org, catalin.marinas@arm.com, dave.hansen@linux.intel.com, dave.hansen@intel.com, hpa@zytor.com, kys@microsoft.com, will@kernel.org, boris.ostrovsky@oracle.com, linux-arch@vger.kernel.org, wei.liu@kernel.org, sstabellini@kernel.org, sthemmin@microsoft.com, xen-devel@lists.xenproject.org, linux-scsi@vger.kernel.org, aneesh.kumar@linux.ibm.com, x86@kernel.org, decui@microsoft.com, hch@lst.de, michael.h.kelley@microsoft.com, mingo@redhat.com, pgonda@google.com, rientjes@google.com, kuba@kernel.org, jejb@linux.ibm.com, martin.b.radev@gmail.com, thomas.lendacky@amd.com, Tianyu.Lan@microsoft.com, arnd@arndb.de, konrad.wilk@oracle.com, haiyangz@microsoft.com, bp@alien8.de, luto@kernel.org, krish.sadhukhan@oracle.com, tglx@linutronix.de, vkuznets@redhat.com, linux-arm-kernel@lists.infradead.org, jgross@suse.com, martin.petersen@oracle.com, saravanand@fb.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, rppt@kernel.org, hannes@cmpxchg.org, ardb@kernel.org, akpm@linux-foundation.org, robin.murphy@arm.com, davem@davemloft.net, kirill.shutemov@linux.intel.com X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On 8/28/2021 1:41 AM, Greg KH wrote: > On Fri, Aug 27, 2021 at 01:21:03PM -0400, Tianyu Lan wrote: >> From: Tianyu Lan >> >> Hyperv provides GHCB protocol to write Synthetic Interrupt >> Controller MSR registers in Isolation VM with AMD SEV SNP >> and these registers are emulated by hypervisor directly. >> Hyperv requires to write SINTx MSR registers twice. First >> writes MSR via GHCB page to communicate with hypervisor >> and then writes wrmsr instruction to talk with paravisor >> which runs in VMPL0. Guest OS ID MSR also needs to be set >> via GHCB page. >> >> Signed-off-by: Tianyu Lan >> --- >> Change since v1: >> * Introduce sev_es_ghcb_hv_call_simple() and share code >> between SEV and Hyper-V code. >> Change since v3: >> * Pass old_msg_type to hv_signal_eom() as parameter. >> * Use HV_REGISTER_* marcro instead of HV_X64_MSR_* >> * Add hv_isolation_type_snp() weak function. >> * Add maros to set syinc register in ARM code. >> --- >> arch/arm64/include/asm/mshyperv.h | 23 ++++++ >> arch/x86/hyperv/hv_init.c | 36 ++-------- >> arch/x86/hyperv/ivm.c | 112 ++++++++++++++++++++++++++++++ >> arch/x86/include/asm/mshyperv.h | 80 ++++++++++++++++++++- >> arch/x86/include/asm/sev.h | 3 + >> arch/x86/kernel/sev-shared.c | 63 ++++++++++------- >> drivers/hv/hv.c | 112 ++++++++++++++++++++---------- >> drivers/hv/hv_common.c | 6 ++ >> include/asm-generic/mshyperv.h | 4 +- >> 9 files changed, 345 insertions(+), 94 deletions(-) >> >> diff --git a/arch/arm64/include/asm/mshyperv.h b/arch/arm64/include/asm/mshyperv.h >> index 20070a847304..ced83297e009 100644 >> --- a/arch/arm64/include/asm/mshyperv.h >> +++ b/arch/arm64/include/asm/mshyperv.h >> @@ -41,6 +41,29 @@ static inline u64 hv_get_register(unsigned int reg) >> return hv_get_vpreg(reg); >> } >> >> +#define hv_get_simp(val) { val = hv_get_register(HV_REGISTER_SIMP); } >> +#define hv_set_simp(val) hv_set_register(HV_REGISTER_SIMP, val) >> + >> +#define hv_get_siefp(val) { val = hv_get_register(HV_REGISTER_SIEFP); } >> +#define hv_set_siefp(val) hv_set_register(HV_REGISTER_SIEFP, val) >> + >> +#define hv_get_synint_state(int_num, val) { \ >> + val = hv_get_register(HV_REGISTER_SINT0 + int_num); \ >> + } >> + >> +#define hv_set_synint_state(int_num, val) \ >> + hv_set_register(HV_REGISTER_SINT0 + int_num, val) >> + >> +#define hv_get_synic_state(val) { \ >> + val = hv_get_register(HV_REGISTER_SCONTROL); \ >> + } >> + >> +#define hv_set_synic_state(val) \ >> + hv_set_register(HV_REGISTER_SCONTROL, val) >> + >> +#define hv_signal_eom(old_msg_type) \ >> + hv_set_register(HV_REGISTER_EOM, 0) > > Please just use real inline functions and not #defines if you really > need it. > OK. Will update. Thanks. _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu