From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE16323A3 for ; Tue, 13 Sep 2022 06:01:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663048875; x=1694584875; h=message-id:date:mime-version:cc:to:references:from: subject:in-reply-to:content-transfer-encoding; bh=LJSJTX5Z4IGDOgD+1HXWmQwXqq1YXqUh+I8TJnnlQmM=; b=MxvRYhsYNYfQKlD6cqBD9kHe9irTd8Nz22Ul6s0+yEa5B9M+aXAsnd+9 I49SlKYeI5mCWqYM1MaaARM2SS+hYt1+vfGQpD42UQ8Z9Wl74CJqVIRyT AdHwhB6KIBCV6khKue1vpGSmx1hUvnTjj373fJLnTZRpKNDKtZNKHwpqJ 7jIakaDlStH6z5ln4oTki/2tgzGY84/SdetglcWiVDps9fslF3yYGM8b2 48WueI7tztLBB0E5U5Nv2vYvauKUanvN9IF9uSs8ix3Hd4Q6znRrV1TF/ Xf1bC1166PTAm9h62NAnYPjfeUCl548uZSajDHXqqxiq5QESuiRYZWnk3 A==; X-IronPort-AV: E=McAfee;i="6500,9779,10468"; a="277779228" X-IronPort-AV: E=Sophos;i="5.93,311,1654585200"; d="scan'208";a="277779228" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Sep 2022 23:01:12 -0700 X-IronPort-AV: E=Sophos;i="5.93,311,1654585200"; d="scan'208";a="646783886" Received: from blu2-mobl3.ccr.corp.intel.com (HELO [10.254.213.188]) ([10.254.213.188]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Sep 2022 23:01:10 -0700 Message-ID: Date: Tue, 13 Sep 2022 14:01:07 +0800 Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.2.2 Cc: baolu.lu@linux.intel.com, Joerg Roedel , Will Deacon , Robin Murphy , "linux-kernel@vger.kernel.org" To: "Tian, Kevin" , "iommu@lists.linux.dev" References: <20220912024826.1684913-1-baolu.lu@linux.intel.com> Content-Language: en-US From: Baolu Lu Subject: Re: [PATCH 1/1] iommu/vt-d: Enable PASID during iommu device probe In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Kevin, On 2022/9/13 11:13, Tian, Kevin wrote: >> From: Lu Baolu >> Sent: Monday, September 12, 2022 10:48 AM >> >> Previously PASID supports on both IOMMU and PCI devices are enabled in >> the >> iommu_dev_enable_feature(dev, IOMMU_DEV_FEAT_SVA) path. It's >> functionally >> correct as the SVA is the only feature that requires PASID setup. However, >> looking ahead, we will add more features that need to enable pasid (for >> example, kernel DMA with PASID, SIOV, VM guest SVA, etc.). It makes more >> sense to enable PASID during iommu probing device. >> >> This enables PASID during iommu probing device and deprecates the >> intel_iommu_enable_pasid() helper. This is safe because the IOMMU >> hardware >> will block any PCI TLP with a PASID prefix if there is no IOMMU domain >> attached to the PASID of the device. >> > > IMHO it's better to enable something only when it's actually required, > e.g. does it make more sense to have a IOMMU_DEV_FEAT_PASID > instead? PASID is a capability (not a feature) of a device. Hence from my point of view, the IOMMU driver could enable it by default as long as the IOMMU can handle transactions with PASID. Currently other PCIe capabilities like ATS and PRI are also handled in this way. > > What this patch does has one problem. It's an intel-iommu driver > internal policy. How can a device driver reliably tell that the pasid > capability has been enabled by the iommu driver? If *necessary*, I do not object to letting the device drivers enable or disable PCI/PASID through an IOMMU interface. In that case, we may need a reference counter, and explicitly tell the device driver that disabling PASID will only take effect when the reference counter becomes 0. Best regards, baolu