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[34.38.181.8]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-454917d57aesm25552833f8f.26.2026.05.11.04.45.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 May 2026 04:45:55 -0700 (PDT) Date: Mon, 11 May 2026 11:45:51 +0000 From: Mostafa Saleh To: Jason Gunthorpe Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, iommu@lists.linux.dev, catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, joro@8bytes.org, jean-philippe@linaro.org, mark.rutland@arm.com, qperret@google.com, tabba@google.com, vdonnefort@google.com, sebastianene@google.com, keirf@google.com Subject: Re: [PATCH v6 04/25] iommu/arm-smmu-v3: Move TLB range invalidation into common code Message-ID: References: <20260501111928.259252-1-smostafa@google.com> <20260501111928.259252-5-smostafa@google.com> <20260501124143.GB6912@ziepe.ca> <20260509232931.GJ9285@ziepe.ca> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20260509232931.GJ9285@ziepe.ca> On Sat, May 09, 2026 at 08:29:31PM -0300, Jason Gunthorpe wrote: > On Thu, May 07, 2026 at 09:40:00AM +0000, Mostafa Saleh wrote: > > But that doesn’t solve the problem, which is: At some point, whether > > eagerly from the page table code, through gather sync or a fancy > > invalidation array, the driver will need to populate a range > > invalidation command (tg, ttl, scale...) and this logic is better > > shared with the main driver which is this patch does. > > My point is this patch doesn't share enough. If you do need to issue > invalidations then share everything below the top level tlbi entry > point and don't try to make a pkvm version of the entire logic just by > ripping out the range logic. > > There is no reason for pkvm to need a different algorithm > here. Especially when you get to supporting ATS and multiple devices > and smmus you may as well just use the whole thing. > > Which is why I suggested to copy the entire call chain into a shared > file Agh, actually this seires doesn't deal with ATS, which I think is wrong, propably we have to issue CMDQ_OP_ATC_INV for the whole space on every S2 invalidation which has to be done per-SID and as it can't be done by VMID :/ or just hide ATS support from host for now, I will look into more for v7. But anyway, we don’t have to share any logic, the kernel driver is quite complicated as it is designed for a different use-case. Doing that makes the hypervisor unnecessary complicated and oversharing this logic makes the kernel driver less maintainable IMO. The hypervisor only needs to share the architecture spec of populating commands. If that’s a problem. I am happy to re-write the RIL part in the hypervisor. It's not that complicated, but I thought it makes sense to share as it is a HW contract. Otherwise, we can break this part into some macros that are called by this function and the hypervisor but that's maybe over-engineered. Thanks, Mostafa > > Jason