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[34.76.60.220]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47f85bb5a46sm25674153f8f.9.2026.07.24.12.26.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 12:26:49 -0700 (PDT) Date: Fri, 24 Jul 2026 19:26:45 +0000 From: Mostafa Saleh To: Jason Gunthorpe Cc: iommu@lists.linux.dev, "Joerg Roedel (AMD)" , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, Robin Murphy , Will Deacon , David Matlack , Pasha Tatashin , patches@lists.linux.dev, Pranjal Shrivastava , Samiullah Khawaja Subject: Re: [PATCH 5/7] iommu/arm-smmu-v3: Move the DMA API comment to flush_iotlb_all Message-ID: References: <0-v1-807e2d1a5efb+e1-iommupt_armv8_jgg@nvidia.com> <5-v1-807e2d1a5efb+e1-iommupt_armv8_jgg@nvidia.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <5-v1-807e2d1a5efb+e1-iommupt_armv8_jgg@nvidia.com> On Mon, Jul 06, 2026 at 01:29:11PM -0300, Jason Gunthorpe wrote: > arm_smmu_tlb_inv_context() is the wrong flush_all for this comment, > it is only called during io-pgtable destruction not during the dma-iommu > operation. Move it to arm_smmu_flush_iotlb_all() which is the flush > that is triggered by the dma-iommu lazy flush thread. > > Signed-off-by: Jason Gunthorpe Reviewed-by: Mostafa Saleh Thanks, Mostafa > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 31 +++++++++++---------- > 1 file changed, 16 insertions(+), 15 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index 5087603ea18e62..dd22c0f881bfba 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -2392,21 +2392,6 @@ static void arm_smmu_tlb_inv_context(void *cookie) > { > struct arm_smmu_domain *smmu_domain = cookie; > > - /* > - * If the DMA API is running in non-strict mode then another CPU could > - * have changed the page table and not invoked any flush op. Instead the > - * other CPU will do an atomic_read() and this CPU will have done an > - * atomic_write(). That handshake is enough to acquire the page table > - * writes from the other CPU. > - * > - * All command execution has a dma_wmb() to release all the in-memory > - * structures written by this CPU, that barrier must also release the > - * writes acquired from all the other CPUs too. > - * > - * There are other barriers and atomics on this path, but the above is > - * the essential mechanism for ensuring that HW sees the page table > - * writes from another CPU before it executes the IOTLB invalidation. > - */ > arm_smmu_domain_inv(smmu_domain); > } > > @@ -4078,6 +4063,22 @@ static void arm_smmu_flush_iotlb_all(struct iommu_domain *domain) > { > struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); > > + /* > + * If the DMA API is running in non-strict mode then another CPU could > + * have changed the page table and not invoked any flush op. Instead the > + * other CPU will do an atomic_read() and this CPU will have done an > + * atomic_write(). That handshake is enough to acquire the page table > + * writes from the other CPU. > + * > + * All command execution has a dma_wmb() to release all the in-memory > + * structures written by this CPU, that barrier must also release the > + * writes acquired from all the other CPUs too. > + * > + * There are other barriers and atomics on this path, but the above is > + * the essential mechanism for ensuring that HW sees the page table > + * writes from another CPU before it executes the IOTLB invalidation. > + */ > + > if (smmu_domain->smmu) > arm_smmu_tlb_inv_context(smmu_domain); > } > -- > 2.43.0 >