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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?pv/QqZM6xjD23Pt7uG99v6NH+bON3Ge47fYBnDsGY1Pd+ZGQ+WQhL7WUaByW?= =?us-ascii?Q?7Y7r0jLcZTpdqbTfg3503DNnvrD8oHwCXIGCxFqRO9W+ITT+eVE4f/AifgcT?= =?us-ascii?Q?pjDbEpBQ4W2GAXi3ixB5VWtm+hGwrJthGelmVahuPEQq4s284k4ukP4kfESM?= =?us-ascii?Q?A8zzu3lgLuECMpZo52zqZDq7I12Z4i2CE51ct6J7JvOH+N0jCEeGr4zhYtjz?= =?us-ascii?Q?oxdM7Z0iSwXYEaMd88V8OLj8WgfHC2al+TmCxY2+eiShKcy+mKcxQqdGIKZe?= =?us-ascii?Q?EQ8jjH68y8CU3a4mMAO+LGcJuMhuLXWh/BHy6+mTgbQO86a/qXXs4lvoWSt5?= =?us-ascii?Q?3fCv2hSHfT6JPBPpiu0bltaJugwEEsoAq0XzH+0P9YpoaW2m179Lw3OJbYht?= =?us-ascii?Q?q1VLePVfH5XMs01iPHmmdVI852+wMeTJ/jFeHM+nxgVemQqSAZbSKZ8/LA5n?= =?us-ascii?Q?pKLcv/Yh4iFeyaOCZt4KhO7UMRXei7bpvGj6s/ne4sEZC5NVhWh0pdFIOsR6?= =?us-ascii?Q?5uikiG71d8mfrYP7STQLZ1Gs8RGD8uzJwCZEbCkiccE7g8TmLZJOqgo3BZ3m?= =?us-ascii?Q?ACFuN9WrUjPG1muCtwRiS410YAoksPN456Cs3E006lXqxsI/a/L3Cd0ey8wv?= =?us-ascii?Q?feL6+Nj8TB2X3cW/AUMZ42rfjAfyY/TP+qLdlO7oixaYCa2Muuj9yNpcj3IE?= =?us-ascii?Q?9pAeiU/K6fnNh5r07ELob3q6DVTLNv1Ig10gzHpPkb9ghw7JSfRtR2QMgC2r?= =?us-ascii?Q?4EQ/2zqrdPlSlGL3/BoFSg6tMCmajrNP1DE+Y1Oj/TuB4AsYtKJEDduFe8Z9?= =?us-ascii?Q?R4zlt5a5nU6nSBh3T7L7+vJ+zy6cMBQ7BuuoMozysavpYaVjN1YmjmPJ4Enk?= =?us-ascii?Q?Dv3DwjqLCZfVAwY2rozUyGmMmlluIXsGY7F2/DaFQoUWzi7TFxVe3kYaadle?= =?us-ascii?Q?nDge/cV1bMw6jKYSIXIKSClW/d3v4BrZv5vFKRL5IhHxmQ17Sbf+IuluSehr?= =?us-ascii?Q?349yn424y/lRq1iliMRCK/syKaEaT3NzPInI0dgLx+L11g1Si5ImkAMfGX/4?= =?us-ascii?Q?rXRfcs1azvxjviK0lqgC4VkQsg/XTnFjpdi5N7Dn9579Y+Cx4XZqQUpetvHI?= =?us-ascii?Q?w1vrewvrLCeYrSvmMvAcrzLFghE7uyalQRoA/DW7PL/2fkTjIEJNB81ZVYCD?= =?us-ascii?Q?453YfXtbkU36vTPV5RU30MTsQTh5Ap6qoG2TjZA5z3gR8vLfpNFaWnPifOWT?= =?us-ascii?Q?0wVNbZTWzA405X8EUD3Iqj2D94p7g3hVlb3yjPpJ8ZntACKuAKETNBIioG93?= =?us-ascii?Q?CXGyXAVt8MHHpxb1PeaLqlBsOksfqawTwgU9rFPKJuOKasKJ/2ELbfY2oFb3?= =?us-ascii?Q?LvQ6VmOmAj5WhR43qb9sI/JAkZGqZhVPzhDwyEUOB1AilPgSmLOltaezJDu+?= =?us-ascii?Q?voeCxx5i+8yQfD0rjYFVuX95lPsDa72zvyxsnz99Urd+o+3N2dU0UgbQXAgk?= =?us-ascii?Q?bY6pXlR8yxqnz6LvHQOUnr1mCiUbSo4dW+neF1IG/DlX9piLtbuOyqMQ2eHA?= =?us-ascii?Q?LwlFpvddT6HFK2PVmfqKG7CSQEaFiwTiELek1PdBMIUHu6Ji6va5LE9HD3Md?= =?us-ascii?Q?C6emvmyc8UmiXeM3F0nDy1NYM61i9XmrTM4rMuTGaInthoTmNxBtLrPMYZo0?= =?us-ascii?Q?x/VxJFWN5IuOEUU/h5YOiUeNVtv/rR4EdvkuJ6F1wYAMJnPqwCKbnWuXJuPP?= =?us-ascii?Q?GlNrpsJUyw=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: afe68d33-5dbb-4a51-8d15-08dee9e59dfa X-MS-Exchange-CrossTenant-AuthSource: LV8PR12MB9620.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Jul 2026 00:42:34.1961 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: nI1ybDEvBt4eu0cTFkI/XucOCrTe786ffpUZjVuedmUWgfzqSevftWl0ddvqeu6t X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6402 On Fri, Jul 24, 2026 at 07:36:16PM +0000, Mostafa Saleh wrote: > On Mon, Jul 06, 2026 at 01:29:06PM -0300, Jason Gunthorpe wrote: > > [ This is the last patch to move SMMUv3 over to the generic page > > table: > > 1) Organize the SMMUv3 invalidation flow so iommupt can use it > > .. > > 2) Use the generic iommu page table for SMMUv3 > > > > It depends on #1 > > > > The whole branch is here: > > https://github.com/jgunthorpe/linux/commits/iommu_pt_arm64/ > > ] > > > > Introduce the generic page table for what the ARM spec calls VMSAv8-64 > > (ie the long 64 bit PTE page table, io-pgtable-arm.c) and use it for > > SMMUv3. ARM is by far the most complex page table of all the ones > > implemented, it has the most runtime behavior variations and a lot of > > features. > > > > Like the othe architectures, the page table itself is supported by a kunit > > compare test that runs operations through both io-pgtable-arm.c and the > > new code then checks for identical PTEs. This is on the github link above > > but I don't intend to merge it. > > > > The existing kunit tests for iommupt will automatically cover the new > > format as well. > > > > This is the final series migrating the SMMUv3 driver over to use the new > > functions and remove io-pgtable-arm.c usage. In principle the other iommu > > drivers that use io-pgtable-arm could be converted someday as well. > > > > Robin once mentioned there were errata about contiguous bits, I only found > > 3673557 and it is mitigated in this design by always using RIL. I'm > > assuming that RIL is always available in SMMUs that are effected by > > 3673557? I have a patch add a FEAT if for contiguous bits if that is > > required. > > > > Jason Gunthorpe (7): > > iommupt: Remove the sanity check for pt_num_items_lg2() at the top > > level > > iommupt/kunit: Skip test configs without supported features > > iommupt: Add the 64 bit ARMv8 page table format > > iommu/arm-smmu-v3: Remove io-pgtable-arm from sva.c > > iommu/arm-smmu-v3: Move the DMA API comment to flush_iotlb_all > > iommu/arm-smmu-v3: Use the generic iommu page table > > iommu: Remove pgsize from iommu_iotlb_gather > > I went through the series, it seems the arm work plug in nicely with > the iommupt stuff, I left some comments around, but I feel that > patches 1,2 and 5 can be sent separately. Yeah, I can probably do that > And patch 8 it too large to review, it would be better to split into > 3-6 patches, I was thinking: base support, dirty tracking, contig bit > aarch32 and kunit. I'd rather not have patches creating unique things that don't need to exist eg a version without contig or something like that. It is too much busy work to go and test all of that. Clean splits like around the kunit and dirty tracking are OK, but I didn't feel it reduces the reviewer burden. But yeah, arm is uniquely large because of it's complexity. Thanks, Jason