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[35.189.192.250]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49d057f4778sm274178525e9.8.2026.09.08.01.39.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2026 01:39:02 -0700 (PDT) Date: Tue, 8 Sep 2026 08:38:58 +0000 From: Mostafa Saleh To: Jason Gunthorpe Cc: linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, jpb@kernel.org, will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, nicolinc@nvidia.com, praan@google.com Subject: Re: [PATCH] iommu/arm-smmu-v3-sva: Relax ASID requirements Message-ID: References: <20260907154928.4012151-1-smostafa@google.com> <20260907184513.GA2543240@ziepe.ca> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20260907184513.GA2543240@ziepe.ca> On Mon, Sep 07, 2026 at 03:45:13PM -0300, Jason Gunthorpe wrote: > On Mon, Sep 07, 2026 at 03:49:28PM +0000, Mostafa Saleh wrote: > > arm_smmu_sva_supported() have some residual checks for ASID from the > > original commit d744f9e6c222 ("iommu/arm-smmu-v3: Check for SVA features") > > > > As DVM was used for TLB invalidation and the ASID of the domain was shared > > with the CPU process. > > > > However, the commit > > d38c28dbefee ("iommu/arm-smmu-v3: Put the SVA mmu notifier in the smmu_domain") > > removed that support. > > > > So matching the SMMU ASID space to the CPU is unnecessary and can be > > relaxed. > > > > Remove the CPU ASID related code, and update the print for the SMMUv3. > > It is OK, but maybe this could also be but under an if > ARM_SMMU_FEAT_BTM? That is never enabled and is a placeholder to for > eventual BTM support. Yes, otherwise SMMUs with BTM would regress in the future. But I’d assume non-BTM SMMUs will still be supported; falling back to SW invalidation? Thanks, Mostafa > > Once we get the last part of the invs code the BTM support can come > back in. > > Jasson