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[34.142.211.105]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2df91444797sm47124675ad.58.2026.09.28.16.59.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Sep 2026 16:59:59 -0700 (PDT) Date: Mon, 28 Sep 2026 23:59:54 +0000 From: Pranjal Shrivastava To: Mostafa Saleh Cc: linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, jgg@ziepe.ca, nicolinc@nvidia.com, Jason Gunthorpe Subject: Re: [PATCH v2 1/5] iommu/arm-smmu-v3: Ensure L2 tables are visible before L1 ptrs Message-ID: References: <20260924085616.300650-1-smostafa@google.com> <20260924085616.300650-2-smostafa@google.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260924085616.300650-2-smostafa@google.com> On Thu, Sep 24, 2026 at 08:56:12AM +0000, Mostafa Saleh wrote: > Commit 6fabce53f6b9 ("iommu/arm-smmu-v3: Add a missing dma_wmb() for hitless STE update") > adds a dma_wmb() to arm_smmu_write_entry() to make sure stream tables > and context descriptors are observed first. > > However, STE L1 table descriptors are configured directly > via WRITE_ONCE(), where before that they were zeroed with memset() > inside dma_direct_alloc() then written to abort in via memset() also > in arm_smmu_init_initial_stes() without a barrier in both cases which > means that the SMMUv3 can observe the allocated table before the > written descriptors causing it to fetch random data. > > Similarly in arm_smmu_write_cd_l1_desc() where the L1 CD is written > after dma_alloc_coherent() with no barriers. > > Add dma_wmb() in both cases. > > Fixes: 48ec83bcbcf5 ("iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices") > Reported-by: Sashiko <> > Reviewed-by: Nicolin Chen > Reviewed-by: Jason Gunthorpe > Signed-off-by: Mostafa Saleh Reviewed-by: Pranjal Shrivastava Thanks, Praan