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Mon, 08 Jun 2026 07:11:16 -0700 (PDT) X-Received: by 2002:a05:6a00:90a7:b0:842:5634:3c1d with SMTP id d2e1a72fcca58-842b0e835d1mr15041493b3a.19.1780927876081; Mon, 08 Jun 2026 07:11:16 -0700 (PDT) Received: from [10.219.56.113] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8428706fa9asm17907958b3a.45.2026.06.08.07.11.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 Jun 2026 07:11:15 -0700 (PDT) Message-ID: Date: Mon, 8 Jun 2026 19:41:10 +0530 Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/6] dt-bindings: iommu: arm,smmu: Document interconnects property To: Dmitry Baryshkov Cc: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org References: <20260526-smmu_interconnect_addition-v2-0-2a6d8ca30d63@oss.qualcomm.com> <20260526-smmu_interconnect_addition-v2-1-2a6d8ca30d63@oss.qualcomm.com> Content-Language: en-US From: Bibek Kumar Patro In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjA4MDEzNCBTYWx0ZWRfX1GjekrdnooC5 EuUDaM+M6WyD46HhKHp/pct5ad7qCSDjiKMoe7uVUWXTelk5eZJ6dHE3FqUrN29IMaw1oVES2C3 4tC/AqhfCtoDolzHpXutBhXOj2JSSujcteuFZN2v/khAEfbSOBkEI8FjVFvRAdK8xQH5CUvrNqZ UyjHgoUlLIG/pD2Ms1Nm5edHBYvroJ9kPUEyj5oerzHSdU3oaFGsPTbsyBV9qD+Q7ZmHFUiOcL3 vszEJ6DmAXBiKfpQTXcnFuUq/CRsPK7LikLe/COcsZNYJQD5LszT235nCACsngyHF0qfH8tbWdQ CFqsOJXrr7lP8uLUX7gCCCNuFoe2T+B8ih+bdtaaebzNiPC+2Kwxlf6uPcg0OgDX0dSRSKhmqPU gKbyhA7DwVBXDfnyPhm2PfrIydPR4o1Edwe33J91+SfcnPc9KUBx0YqgXWZGCE66wfA3PI/QcNC zZlxqFkKPUcHJn8w4VA== X-Proofpoint-ORIG-GUID: Lop9PVNz9CFKRz5Itf3rHdgwun2S1vJp X-Proofpoint-GUID: Lop9PVNz9CFKRz5Itf3rHdgwun2S1vJp X-Authority-Analysis: v=2.4 cv=Z7rc2nRA c=1 sm=1 tr=0 ts=6a26cd85 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=nHMyhPlvQ-XDY_K2CzoA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-08_03,2026-06-05_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 bulkscore=0 suspectscore=0 adultscore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606080134 On 6/8/2026 7:18 PM, Dmitry Baryshkov wrote: > On Tue, May 26, 2026 at 08:12:02PM +0530, Bibek Kumar Patro wrote: >> Some SoC implementations require a bandwidth vote on an interconnect >> path before the SMMU register space is accessible. Add the optional >> 'interconnects' property to the binding to allow platform DT nodes >> to describe this path. >> >> Signed-off-by: Bibek Kumar Patro >> --- >> .../devicetree/bindings/iommu/arm,smmu.yaml | 27 ++++++++++++++++++++++ >> 1 file changed, 27 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml >> index 06fb5c8e7547cb7a92823adc2772b94f747376a6..3a677ff1a18fcdf5c0ca9ec8a017d41f9eb5ff09 100644 >> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml >> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml >> @@ -243,6 +243,13 @@ properties: >> minItems: 1 >> maxItems: 3 >> >> + interconnects: >> + maxItems: 1 >> + description: >> + Interconnect path to the SMMU register space. Required on SoCs >> + where the SMMU registers are only accessible after a bandwidth >> + vote has been placed on the interconnect fabric. >> + >> nvidia,memory-controller: >> description: | >> A phandle to the memory controller on NVIDIA Tegra186 and later SoCs. >> @@ -602,6 +609,26 @@ allOf: >> clock-names: false >> clocks: false >> >> + - if: >> + properties: >> + compatible: >> + items: >> + - enum: >> + - qcom,qcs615-smmu-500 >> + - qcom,qcs8300-smmu-500 >> + - qcom,sa8775p-smmu-500 >> + - qcom,sc7280-smmu-500 > > Only these platforms have the interconnect which needs to be voted > upon? > Apart from these QLI platforms, sm8650 and kaanapali would also need the interconnect support as per the SoC documentation, but it hasn't been tested yet [1]. So haven't added it as part of the ongoing series, hence as mentioned [2] this list might grow to accomodate other platforms. [1]: https://lore.kernel.org/all/a1db573b-bcb4-44a5-89b6-6d1c76f4a18a@oss.qualcomm.com/ [2]: https://lore.kernel.org/all/0ded611e-1932-470c-8e80-9a5e94268583@oss.qualcomm.com/ >> + - const: qcom,adreno-smmu >> + - const: qcom,smmu-500 >> + - const: arm,mmu-500 >> + then: >> + properties: >> + interconnects: >> + maxItems: 1 >> + else: >> + properties: >> + interconnects: false >> + >> - if: >> properties: >> compatible: >> >> -- >> 2.34.1 >> >