From mboxrd@z Thu Jan 1 00:00:00 1970 From: Lu Baolu Subject: Re: [PATCH v3 03/10] iommu/sva: Manage process address spaces Date: Wed, 26 Sep 2018 07:33:35 +0800 Message-ID: References: <20180920170046.20154-1-jean-philippe.brucker@arm.com> <20180920170046.20154-4-jean-philippe.brucker@arm.com> <09933fce-b959-32e1-b1f3-0d4389abf735@linux.intel.com> <20180925132627.vbdotr23o7lqrmnd@8bytes.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20180925132627.vbdotr23o7lqrmnd-zLv9SwRftAIdnm+yROfE0A@public.gmane.org> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Joerg Roedel Cc: linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, will.deacon-5wv7dgnIgG8@public.gmane.org, okaya-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, ashok.raj-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, Jean-Philippe Brucker , kevin.tian-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, alex.williamson-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, robin.murphy-5wv7dgnIgG8@public.gmane.org, ilias.apalodimas-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, liguozhu-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org, christian.koenig-5C7GfCeVMHo@public.gmane.org List-Id: iommu@lists.linux-foundation.org Hi Joerg, On 09/25/2018 09:26 PM, Joerg Roedel wrote: > On Tue, Sep 25, 2018 at 11:15:40AM +0800, Lu Baolu wrote: >> This might be problematic for vt-d (and other possible arch's which use >> PASID other than SVA). When vt-d iommu works in scalable mode, a PASID >> might be allocated for: >> >> (1) SVA >> (2) Device Assignable Interface (might be a mdev or directly managed >> within a device driver). >> (3) SVA in VM guest >> (4) Device Assignable Interface in VM guest >> >> So we can't expect that an io_mm pointer was associated with each PASID. >> And this code might run into problem if the pasid is allocated for >> usages other than SVA. > > So all of these use-cases above should work in parallel on the same > device, just with different PASIDs? No. It's not required. > Or is a device always using only one > of the above modes at the same time? A device might use one or multiple modes described above at the same time. Best regards, Lu Baolu