From: Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org>
To: Jayachandran C
<jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>,
Bjorn Helgaas <helgaas-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Alex Williamson
<alex.williamson-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org
Cc: Jon Masters <jcm-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Subject: Re: [PATCH v4 2/2] PCI: quirks: Fix ThunderX2 dma alias handling
Date: Mon, 3 Apr 2017 16:07:53 +0100 [thread overview]
Message-ID: <b44e6df5-4840-ecb4-59c6-b4bc474ad28c@arm.com> (raw)
In-Reply-To: <1491225304-3559-3-git-send-email-jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
On 03/04/17 14:15, Jayachandran C wrote:
> The Cavium ThunderX2 arm64 SoCs (called Broadcom Vulcan earlier), the PCI
> topology is slightly unusual. For a multi-node system, it looks like:
>
> [node level PCI bridges - one per node]
> [SoC PCI devices with MSI-X but no IOMMU]
> [PCI-PCIe "glue" bridges - upto 14, one per real port below]
> [PCIe real root ports associated with IOMMU and GICv3 ITS]
> [External PCI devices connected to PCIe links]
Since it's not entirely obvious, what does the actual DT - or IORT if
you must ;) - topology for this look like? I can't help thinking that
either it's inaccurate, or that this is going to expose a shortcoming in
pci_dma_configure() which breaks things - unless I'm missing something,
isn't find_pci_root_bus() going to go all the way up to the top-level
glue bridge and pick up the wrong firmware node (if any) for the
appropriate DMA properties?
Robin.
> The top two levels of bridges should have introduced aliases since they
> are PCI and PCI/PCIe bridges, but in the case of ThunderX2 they do not.
> In the case of external PCIe devices, the "real" root ports are connected
> to the SMMU and the GIC ITS, so PCI-PCIe bridge does not introduce an
> alias. The SoC PCI devices are directly connected to the GIC ITS, so the
> node level bridges do not introduce an alias either.
>
> To handle this quirk, we mark the real PCIe root ports and node level
> PCI bridges with the flag PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT. With this,
> pci_for_each_dma_alias() works correctly for external PCIe devices and
> SoC PCI devices.
>
> For the current revision of Cavium ThunderX2, the VendorID and Device ID
> are from Broadcom Vulcan (14e4:90XX).
>
> Signed-off-by: Jayachandran C <jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
> ---
> drivers/pci/quirks.c | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index 6736836..564a84a 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -3958,6 +3958,20 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
> DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
>
> /*
> + * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are
> + * associated not at the root bus, but at a bridge below. This quirk flag
> + * will ensure that the aliases are identified correctly.
> + */
> +static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev)
> +{
> + pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT;
> +}
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000,
> + quirk_bridge_cavm_thrx2_pcie_root);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084,
> + quirk_bridge_cavm_thrx2_pcie_root);
> +
> +/*
> * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
> * class code. Fix it.
> */
>
next prev parent reply other threads:[~2017-04-03 15:07 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-03 13:15 [PATCH v4 0/2] Handle Cavium ThunderX2 PCI topology quirk Jayachandran C
2017-04-03 13:15 ` [PATCH v4 2/2] PCI: quirks: Fix ThunderX2 dma alias handling Jayachandran C
[not found] ` <1491225304-3559-3-git-send-email-jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
2017-04-03 15:07 ` Robin Murphy [this message]
[not found] ` <b44e6df5-4840-ecb4-59c6-b4bc474ad28c-5wv7dgnIgG8@public.gmane.org>
2017-04-04 11:50 ` Jayachandran C
2017-04-04 14:28 ` Robin Murphy
[not found] ` <2f6b5c29-c985-dbfc-8738-cbc9bd85e408-5wv7dgnIgG8@public.gmane.org>
2017-04-10 11:38 ` Jayachandran C
2017-04-13 6:43 ` Jon Masters
2017-04-11 1:28 ` Bjorn Helgaas
2017-04-11 7:10 ` Jayachandran C
2017-04-11 13:41 ` Bjorn Helgaas
[not found] ` <20170411134125.GA31773-1RhO1Y9PlrlHTL0Zs8A6p5iNqAH0jzoTYJqu5kTmcBRl57MIdRCFDg@public.gmane.org>
2017-04-11 15:27 ` Jayachandran C
2017-04-11 15:43 ` Jon Masters
2017-04-12 16:21 ` Bjorn Helgaas
[not found] ` <20170412162118.GC25197-1RhO1Y9PlrlHTL0Zs8A6p5iNqAH0jzoTYJqu5kTmcBRl57MIdRCFDg@public.gmane.org>
2017-04-12 18:10 ` Jayachandran C
2017-04-12 19:11 ` Bjorn Helgaas
[not found] ` <20170412191138.GH25197-1RhO1Y9PlrlHTL0Zs8A6p5iNqAH0jzoTYJqu5kTmcBRl57MIdRCFDg@public.gmane.org>
2017-04-12 20:41 ` Jayachandran C
2017-04-12 23:18 ` Bjorn Helgaas
2017-04-11 15:34 ` Robin Murphy
[not found] ` <1491225304-3559-1-git-send-email-jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
2017-04-03 13:15 ` [PATCH v4 1/2] PCI: Add device flag PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT Jayachandran C
[not found] ` <1491225304-3559-2-git-send-email-jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
2017-04-03 14:59 ` Robin Murphy
2017-04-11 13:44 ` [PATCH v4 0/2] Handle Cavium ThunderX2 PCI topology quirk Bjorn Helgaas
[not found] ` <CABhMZUXNhKSQALAHP1CBNfWMuw0J0XQ2rzusP4WR_HHH9ox5Yw@mail.gmail.com>
[not found] ` <CABhMZUXh=X5k1DQhUcaXD4t9GWfXms80xWV7sAh0ZXD8YK794g@mail.gmail.com>
[not found] ` <CABhMZUXh=X5k1DQhUcaXD4t9GWfXms80xWV7sAh0ZXD8YK794g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-04-11 14:23 ` Bjorn Helgaas
2017-04-11 16:01 ` David Daney
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