From: Steven Price <steven.price@arm.com>
To: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>,
linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org,
iommu@lists.linux-foundation.org
Cc: jon@solid-run.com, linuxarm@huawei.com, guohanjun@huawei.com,
yangyicong@huawei.com, Sami.Mujawar@arm.com,
robin.murphy@arm.com, wanghuiqiang@huawei.com
Subject: Re: [PATCH v6 8/9] iommu/arm-smmu: Get associated RMR info and install bypass SMR
Date: Fri, 16 Jul 2021 14:52:43 +0100 [thread overview]
Message-ID: <b73d3408-7b2e-4cab-3b8c-efc22d08d99e@arm.com> (raw)
In-Reply-To: <20210716083442.1708-9-shameerali.kolothum.thodi@huawei.com>
On 16/07/2021 09:34, Shameer Kolothum wrote:
> From: Jon Nettleton <jon@solid-run.com>
>
> Check if there is any RMR info associated with the devices behind
> the SMMU and if any, install bypass SMRs for them. This is to
> keep any ongoing traffic associated with these devices alive
> when we enable/reset SMMU during probe().
>
> Signed-off-by: Jon Nettleton <jon@solid-run.com>
> Signed-off-by: Steven Price <steven.price@arm.com>
> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
> ---
> drivers/iommu/arm/arm-smmu/arm-smmu.c | 48 +++++++++++++++++++++++++++
> 1 file changed, 48 insertions(+)
>
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c
> index f22dbeb1e510..e9fb3d962a86 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c
> @@ -2063,6 +2063,50 @@ err_reset_platform_ops: __maybe_unused;
> return err;
> }
>
> +static void arm_smmu_rmr_install_bypass_smr(struct arm_smmu_device *smmu)
> +{
> + struct list_head rmr_list;
> + struct iommu_resv_region *e;
> + int i, cnt = 0;
> + u32 reg;
> +
> + INIT_LIST_HEAD(&rmr_list);
> + if (iommu_dma_get_rmrs(dev_fwnode(smmu->dev), &rmr_list))
> + return;
> +
> + /*
> + * Rather than trying to look at existing mappings that
> + * are setup by the firmware and then invalidate the ones
> + * that do no have matching RMR entries, just disable the
> + * SMMU until it gets enabled again in the reset routine.
> + */
> + reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sCR0);
> + reg &= ~ARM_SMMU_sCR0_CLIENTPD;
This looks backwards, the spec states:
Client Port Disable. The possible values of this bit are:
0 - Each SMMU client access is subject to SMMU translation, access
control, and attribute generation.
1 - Each SMMU client access bypasses SMMU translation, access control,
and attribute generation.
This bit resets to 1.
And indeed with the current code if sCR0_USFCFG was set when
sCR0_CLIENTPD is cleared then I get a blank screen until the smmu is reset.
So I believe this should be ORing in the value, i.e.
reg |= ARM_SMMU_sCR0_CLIENTPD;
And in my testing that works fine even if sCR0_USFCFG is set.
Steve
> + arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sCR0, reg);
> +
> + list_for_each_entry(e, &rmr_list, list) {
> + u32 sid = e->fw_data.rmr.sid;
> +
> + i = arm_smmu_find_sme(smmu, sid, ~0);
> + if (i < 0)
> + continue;
> + if (smmu->s2crs[i].count == 0) {
> + smmu->smrs[i].id = sid;
> + smmu->smrs[i].mask = 0;
> + smmu->smrs[i].valid = true;
> + }
> + smmu->s2crs[i].count++;
> + smmu->s2crs[i].type = S2CR_TYPE_BYPASS;
> + smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT;
> +
> + cnt++;
> + }
> +
> + dev_notice(smmu->dev, "\tpreserved %d boot mapping%s\n", cnt,
> + cnt == 1 ? "" : "s");
> + iommu_dma_put_rmrs(dev_fwnode(smmu->dev), &rmr_list);
> +}
> +
> static int arm_smmu_device_probe(struct platform_device *pdev)
> {
> struct resource *res;
> @@ -2189,6 +2233,10 @@ static int arm_smmu_device_probe(struct platform_device *pdev)
> }
>
> platform_set_drvdata(pdev, smmu);
> +
> + /* Check for RMRs and install bypass SMRs if any */
> + arm_smmu_rmr_install_bypass_smr(smmu);
> +
> arm_smmu_device_reset(smmu);
> arm_smmu_test_smr_masks(smmu);
>
>
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next prev parent reply other threads:[~2021-07-16 13:52 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-16 8:34 [PATCH v6 0/9] ACPI/IORT: Support for IORT RMR node Shameer Kolothum
2021-07-16 8:34 ` [PATCH v6 1/9] iommu: Introduce a union to struct iommu_resv_region Shameer Kolothum
2021-07-16 8:34 ` [PATCH v6 2/9] ACPI/IORT: Add support for RMR node parsing Shameer Kolothum
2021-07-16 8:34 ` [PATCH v6 3/9] iommu/dma: Introduce generic helper to retrieve RMR info Shameer Kolothum
2021-07-16 8:34 ` [PATCH v6 4/9] ACPI/IORT: Add a helper to retrieve RMR memory regions Shameer Kolothum
2021-07-16 8:34 ` [PATCH v6 5/9] iommu/arm-smmu-v3: Introduce strtab init helper Shameer Kolothum
2021-07-16 8:34 ` [PATCH v6 6/9] iommu/arm-smmu-v3: Refactor arm_smmu_init_bypass_stes() to force bypass Shameer Kolothum
2021-07-16 8:34 ` [PATCH v6 7/9] iommu/arm-smmu-v3: Get associated RMR info and install bypass STE Shameer Kolothum
2021-07-16 8:34 ` [PATCH v6 8/9] iommu/arm-smmu: Get associated RMR info and install bypass SMR Shameer Kolothum
2021-07-16 13:52 ` Steven Price [this message]
2021-07-16 20:40 ` Jon Nettleton
2021-07-16 8:34 ` [PATCH v6 9/9] iommu/dma: Reserve any RMR regions associated with a dev Shameer Kolothum
2021-07-19 13:45 ` [PATCH v6 0/9] ACPI/IORT: Support for IORT RMR node Laurentiu Tudor
2021-07-27 6:51 ` Shameerali Kolothum Thodi
2021-08-02 9:22 ` joro
2021-07-27 8:32 ` Hanjun Guo
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